CMOS FABRICATION

•Lithography

•Etching

•Oxidation

•Doping

•Deposition

An Overview of Microfabrication Processes

• Photolithography: Process by which the surface of a substrate can be patterned with micron size features. Photolithography requires a photoresist layer to be put on the substrate, a photomask that has the required pattern and a UV light source to expose the photoresist.

• The photoresist is a photographic emulsion that when exposed to UV light changes its chemical structure. For example region exposed may be cross linked and hardened. Developers exist for removing the non-hardened regions of photoresist. Photoresist is chemically resistant to chemicals that etch inorganic materials (especially buffered HF) and can be removed easily by organic removers such as acetone.

• Photomask is a piece of glass with a photographic emulsion on it. When exposed to light or to e-beam the photographic emulsion turns black and absorbs the UV light. Photomasks are typically generated today by e-beam lithography machines with feature sizes down to 0.1mm.

• Mask Aligner is a special instrument used to align different mask layers corresponding to different photolithographic steps on the substrate such that complex devices can be fabricated

• Oxide growth is process which results in the formation of a SiO2 layer on the top of the silicon circuit. This oxide layer can be used as a mask for subsequent processing steps or can be used as an electrical component within a transistor such as the gate oxide of a MOSFET. When used as a mask its chemical properties are critical and it can be deposited by chemical vapor deposition, that is by decomposing silane gas in a reactor in an oxygen rich environment and depositing the formed SiO2 molecules on silicon typically at lower temperatures e.g. 350oC. When used as gate oxide or as an electrical insulator, the electrical properties of the SiO2 layer are critical. In that case the SiO2 layer is grown by oxidizing the silicon wafer surface by bringing it in contact with oxygen in a high temperature furnace e.g. @1100oC.

• Oxide etching processes involve the removal of SiO2 layers from the surface of the silicon substrate usually using a photoresist mask to pattern the SiO2 layer. This can be done by wet etching, (by dipping the photoresist patterned substrate into buffered HF, where the acid will attack the exposed regions of SiO2 ) or by dry etching (where a chemical gas plasma will attack and etch the exposed SiO2 regions).

• Doping is the process of introducing dopant atoms into silicon for creating n and p type regions. Doping can be realized by diffusion or by ion implantation.

• The diffusion process involves bringing the dopant sources such as Phosphorous or Boron in close contact with the silicon substrate in a diffusion furnace at temperatures above 9000C. The dopant atoms will then diffuse into the exposed silicon regions whereas the SiO2 protected regions will not be doped. Typically the diffusion process is followed by a high temperature (1100oC) oxidation process to drive in the dopant atoms further into the substrate.

• The ion implantation process uses an ion implanter that accelerates the dopant atoms in vacuum such that when they encounter the silicon substrate they have enough energy to penetrate the unprotected regions of the silicon substrate. Subsequently a higher temperature annealing (600oC) step is required to activate the dopant atoms and restore the crystal quality of the silicon surface.

• Metallization is generally carried out by evaporating aluminum and depositing it on a silicon wafer. The process of evaporation is carried out in a vacuum chamber where an aluminum source is heated. The evaporating Aluminum atoms gain enough energy in vacuum to freely move in the chamber and attach themselves to cooler regions including the silicon substrates. The thin Aluminum layer can then be patterned using a photolithographic step.

PHOTOLITHOGRAPHY

PHOTOLITHOGRAPHY

The process of selectively removing

un-exposed (or exposed)

photoresist is called development.

The photoresist is patterned

During etching of the desired

material, patterned photoresist acts

as a mask to protect desired regions

of the material being etched

The pattern of the original mask is

transferred to the desired material

by means of photolithography

Using photolithography to pattern polysilicon with positive photoresist

PHOTOLITHOGRAPHY

6

Etching

OXIDATION

8

Doping by Diffusion or Ion Implantation

Diffusion is done at high temperatures 800-1200C while ion implantaion

can be done at low temperature 500-800C

DEPOSITION

Metal deposition by evaporation

EPITAXY

IC processing loop

Strip Field oxide Diffuse, oxidize open gate

Grow gate oxide, open contacts Metallize and pattern

STANDARD METAL GATE MOS TRANSISTOR

LAYOUT AND PROCESS

Strip Field oxide Diffuse, oxidize open gate region

Grow gate oxide, open contacts Metallize and pattern

1 2

3 4

STANDARD METAL GATE MOS TRANSISTOR LAYOUT AND PROCESS

The PMOS fabrication

• Around 1970, pMOS circuits with aluminum gate metal and wiring were dominant.

• The primary problem at the time was threshold voltage control. Positively charged ions in the

oxide decreased the threshold voltage of the devices. p-type MOSFETs were therefore the device

of choice despite the lower hole mobility, since they would still be enhancement-type devices even

when charge was present.

• Thermal oxidation of the silicon in an oxygen or water vapor atmosphere provided a quality gate

oxide with easily controlled thickness. The same process was also used to provide a high-

temperature mask for the diffusion process and a passivation and isolation layer. Some people

claim that the quality and versatility of silicon’s oxide made silicon the preferred semiconductor

over germanium.

• The oxide was easily removed in hydrofluoric acid (HF), without removing the underlying silicon,

thanks to the high selectivity if the etch

• Aluminum was evaporated over the whole wafer and then etched yielding both the gate metal and

the metal wiring connecting the devices. A small amount of copper (~2%) was added to make the

aluminum more resistant to electromigration. Electromigration is the movement of atoms due to

the impact with the electrons carrying the current through the wire. This effect can cause open

circuits and is therefore a well-known reliability problem.

• Annealing the metal in a nitrogen/hydrogen (N2/H2) ambient was used to improve the metal-

semiconductor contact and to reduce the surface state density at the semiconductor/gate-oxide

interface.

UCSD Esener 5”. 14

SELF ALIGNED GATE MOS TRANSISTOR LAYOUT

AND PROCESS

Strip Field oxide Regrow gate oxide Deposit gate

Oxidize and open contact holes Metallize and pattern

Pattern gate and oxide

Diffuse

SELF ALIGNED GATE MOS TRANSISTOR LAYOUT

AND PROCESS

Strip Field oxide & Regrow gate oxide Deposit gate & pattern , diffuse

Oxidize and open contact holes Metallize and pattern

1 2

3 4

INVERTER LAYOUT

METAL GATE, POLY-GATE,

•Provides better noise margins

•Higher speed (small Cgs and NL pull up)

•More levels of interconnects-smaller area

•But requires one additional mask layer and poly deposition

CMOS INVERTER LAYOUT

OutIn

VDD

PMOS

NMOS

CMOS circuits have a lower power dissipation and larger operating margin. It

was only when the number of transistors per chip became much larger that the

inherent advantages of CMOS circuits became clear.

Silicide Silicide n+ Poly Gate oxide p+ Poly

Shallow Trench Isolation

n-well

STI

Source-drain

STI n + n+

p-doping

Source-drain extensions

p+ p+

n-doping

extensions

MODERN HP CMOS INVERTER LAYOUT

NMOS

PMOS POLY GATE

VDD GND

n-tub

SIMPLIFIED CMOS FABRICATION

Most changes were introduced to provide superior performance, better reliability and

higher yield.

Increasing the number of transistors:

• Reduction of the gate length. A gate length reduction provides a shorter transit time

and hence a faster device. This reduction is linked to a reduction of the minimum

feature size and therefore yields smaller transistors as well as a larger number of

transistors on a chip with a given size. I

• Making larger chips, so that the number of transistors per chip increased even faster.

• Increasing wafer size to accommodate the larger chips while reducing the loss due to

partial chips at the wafer periphery. Larger wafers further reduce the cost per chip as

more chips can be accommodated on a single wafer

Circuit Improvements

• Early on, the pMOS devices were replaced with nMOS transistors because of the

better electron mobility. Enhancement-mode loads were replaced by depletion-mode

loads yielding faster logic circuits with larger operating margins.

Manufacturing and circuit Improvements

UCSD Esener 5”. 21

Process improvements can be split into those aimed at improving the circuit

performance and those improving the manufacturability and reliability.

• Self-aligned poly-silicon gate process was introduced before CMOS and marked

the beginning of modern day MOSFETs. The self-aligned structure, is obtained by

using the gate as the mask for the source-drain implant. Since the crystal damage

caused by the high-energy ions must be annealed at high temperature (~800 C), an

aluminum gate could no longer be used. Doped poly-silicon was found to be a very

convenient gate material since it withstands the high anneal temperature and can be

oxidized just like silicon.

• The self-aligned process lowers the parasitic capacitance between gate and drain

and therefore improves the high-frequency performance and switching time.

• Addition of a silicide layer on top of the gate reduces the gate resistance while still

providing a quality implant mask. The self-aligned process also reduced the transistor

size and hence increased the density.

• Local oxidation isolation structure (LOCOS), replaced the field oxide. A Si3N4 layer

is used to prevent the oxidation in the MOSFET region. This oxide provides an implant

mask and contact hole mask yielding an even more compact device.

Process Improvements aiming at

circuit performance I

UCSD Esener 5”. 22

• Chemical vapor deposition (CVD) of insulating layers replaced thermal

oxidation since it does not consume the underlying silicon andbecause there is

no limit to the obtainable thickness since materials other than SiO2 (for instance

Si3N4) can be deposited.

• Ion implantation replaced diffusion because of its superior control and

uniformity.

• Dry etching including plasma etching, reactive ion etching (RIE) and ion beam

etching has replaced wet chemical etching. These etch processes provide better

etch rate uniformity and control as well as very pronounced anisotropic etching.

• Sputtering of metals has completely replaced evaporation. Sputtering typically

provides better adhesion and thickness control.

• Deuterium anneal is a recent modification of the standard hydrogen anneal,

which passivates the surface states. The use of deuterium therefore reduces the

increase of the surface state density due to hot-electron impact.

Process Improvements aimed at

manufacturability and reliability:

UCSD Esener 5”. 23

TEM Cross-section

N-well CMOS fab. process

Typ. CMOS Fabrication steps I

CMOS Fab. Steps II

CMOS Fab. Steps III

CMOS Fab. Steps IV

Summary of CMOS Fabrication