13.06.20 11:57CSCI 150 Introduction to Digital and Computer

System Design Lecture 3: Combinational Logic Design III

Jetic Gū2020 Summer Semester (S2)

Overview• Focus: Logic Functions

• Architecture: Combinatory Logical Circuits

• Textbook v4: Ch3 3.6; v5: Ch3 3.1, 3.4

• Core Ideas:

1. Terminologies: Value-Fixing, Transferring, Inverting, Enabler

2. Decoder

Systematic Design Procedures1. Specification: Write a specification for the circuit

2. Formulation: Derive relationship between inputs and outputs of the systeme.g. using truth table or Boolean expressions

3. Optimisation: Apply optimisation, minimise the number of logic gates and literals required

4. Technology Mapping: Transform design to new diagram using available implementation technology

5. Verification: Verify the correctness of the final design in meeting the specifications

Review

P0 Review

Systematic Design Procedures

• Hierarchical Design

• Divide complex designs into smaller functional blocks, then apply the same 5-step design procedures for each block

• Reusable, easier and more efficient Implementation

Review

P0 Review

Value-Fixing, Transferring, Inverting,

Enabler

Summary

P1 Elementary Func.

Elementary Combinational Logic Functions

Value-Fixing, Transferring, and Inverting

Concep

t

P1 Elementary Func.

① Value-Fixing: giving a constant value to a wire

• ; ;

② Transferring: giving a variable (wire) value from another variable (wire)

• ;

③ Inverting: inverting the value of a variable

•

F = 0 F = 1

F = X

F = X

Value-Fixing, Transferring, and Inverting

Concep

t

P1 Elementary Func.

3-4 / Rudimentary Logic Functions 123

consequence, logic gates are not involved in the implementation of these operations. Inverting involves only one logic gate per variable, and enabling involves one or two logic gates per variable.

Value-Fixing, Transferring, and Inverting

If a single-bit function depends on a single variable X, four different functions are possible. Table 3-1 gives the truth tables for these functions. The !rst and last col-umns of the table assign either constant value 0 or constant value 1 to the function, thus performing value !xing. In the second column, the function is simply the input variable X, thus transferring X from input to output. In the third column, the func-tion is X, thus inverting input X to become output X.

The implementations for these four functions are given in Figure 3-7. Value !x-ing is implemented by connecting a constant 0 or constant 1 to output F, as shown in Figure 3-7(a). Figure 3-7(b) shows alternative representations used in logic schemat-ics. For the positive logic convention, constant 0 is represented by the electrical ground symbol and constant 1 by a power-supply voltage symbol. The latter symbol is labeled with either VCC or VDD. Transferring is implemented by a simple wire con-necting X to F as in Figure 3-7(c). Finally, inverting is represented by an inverter which forms F = X from input X, as shown in Figure 3-7(d).

Multiple-Bit Functions

The functions de!ned so far can be applied to multiple bits on a bitwise basis. We can think of these multiple-bit functions as vectors of single-bit functions. For example, suppose that we have four functions, F3, F2, F1, and F0, that make up a four-bit func-tion F. We can order the four functions with F3 as the most signi!cant bit and F0 the

TABLE 3-1Functions of One Variable

X F = 0 F = X F = X F = 1

0 0 0 1 11 0 1 0 1

0

1

(a)

V

F ! 1

F ! 0

F ! 1

F ! 0

F ! X

F ! X

CC or VDD

(b)

X(c)

X

(d)

FIGURE 3-7Implementation of Functions of a Single Variable X

M03_MANO0637_05_SE_C03.indd 123 23/01/15 1:51 PM

① Value-Fixing① Value-Fixing

② Transferring

③ Inverting

Vector Denotation

Concep

t

P1 Elementary Func.

④ Multiple-bit Function

• Functions we’ve seen so far has only one-bit output: 0/1

• Certain functions may have -bit output

• , each is a one-bit function

• Curtain Motor Control Circuit:

n

F(n − 1 : 0) = (Fn−1, Fn−2, . . . , F0) Fi

F = (FMotor1, FMotor2

, FLight)

Vector Denotation

Concep

t

P1 Elementary Func. 124 CHAPTER 3 / COMBINATIONAL LOGIC!DESIGN

least signi!cant bit, providing the vector F = (F3, F2, F1, F0). Suppose that F consists of rudimentary functions F3 = 0, F2 = 1, F1 = A, and F0 = A. Then we can write F as the vector (0, 1, A, A). For A = 0, F = (0, 1, 0, 1) and for A = 1, F = (0, 1, 1, 0). This multiple-bit function can be referred to as F(3:0) or simply as F and is imple-mented in Figure 3-8(a). For convenience in schematics, we often represent a set of multiple, related wires by using a single line of greater thickness with a slash, across the line. An integer giving the number of wires represented accompanies the slash as shown in Figure 3-8(b). In order to connect the values 0, 1, X, and X to the appropri-ate bits of F, we break F up into four wires, each labeled with the bit of F. Also, in the process of transferring, we may wish to use only a subset of the elements in F—for example, F2 and F1. The notation for the bits of F can be used for this purpose, as shown in Figure 3-8(c). In Figure 3-8(d), a more complex case illustrates the use of F3, F1, F0 at a destination. Note that since F3, F1, and F0 are not all together, we cannot use the range notation F(3:0) to denote this subvector. Instead, we must use a combi-nation of two subvectors, F(3), F(1:0), denoted by subscripts 3, 1:0. The actual nota-tion used for vectors and subvectors varies among the schematic drawing tools or HDL tools available. Figure 3-8 illustrates just one approach. For a speci!c tool, the documentation should be consulted.

Value !xing, transferring, and inverting have a variety of applications in logic design. Value !xing involves replacing one or more variables with constant values 1 and 0. Value !xing may be permanent or temporary. In permanent value !xing, the value can never be changed. In temporary value !xing, the values can be changed, often by mechanisms somewhat different from those employed in ordi-nary logical operation. A major application of !xed and temporary value !xing is in programmable logic devices. Any logic function that is within the capacity of the programmable device can be implemented by !xing a set of values, as illustrated in the next example.

EXAMPLE 3-4 Lecture-Hall Lighting Control Using Value Fixing

The Problem: The design of a part of the control for the lighting of a lecture hall speci!es that the switches that control the normal lights be programmable. There are to be three different modes of operation for the two switches. Switch P is on the po-dium in the front of the hall and switch R is adjacent to a door at the rear of the

0 F3

1 F2

A F1

A F0

(a)

0

1

A

A

1

2 34

F

0

(b)

4 2:1 F(2:1)2

F(c)

4 3,1:0 F(3), F(1:0)3

F(d)

FIGURE 3-8Implementation of Multibit Rudimentary Functions

M03_MANO0637_05_SE_C03.indd 124 23/01/15 1:51 PM

Vector Denotation

Concep

t

P1 Elementary Func.

1. These two are equivalent

124 CHAPTER 3 / COMBINATIONAL LOGIC!DESIGN

least signi!cant bit, providing the vector F = (F3, F2, F1, F0). Suppose that F consists of rudimentary functions F3 = 0, F2 = 1, F1 = A, and F0 = A. Then we can write F as the vector (0, 1, A, A). For A = 0, F = (0, 1, 0, 1) and for A = 1, F = (0, 1, 1, 0). This multiple-bit function can be referred to as F(3:0) or simply as F and is imple-mented in Figure 3-8(a). For convenience in schematics, we often represent a set of multiple, related wires by using a single line of greater thickness with a slash, across the line. An integer giving the number of wires represented accompanies the slash as shown in Figure 3-8(b). In order to connect the values 0, 1, X, and X to the appropri-ate bits of F, we break F up into four wires, each labeled with the bit of F. Also, in the process of transferring, we may wish to use only a subset of the elements in F—for example, F2 and F1. The notation for the bits of F can be used for this purpose, as shown in Figure 3-8(c). In Figure 3-8(d), a more complex case illustrates the use of F3, F1, F0 at a destination. Note that since F3, F1, and F0 are not all together, we cannot use the range notation F(3:0) to denote this subvector. Instead, we must use a combi-nation of two subvectors, F(3), F(1:0), denoted by subscripts 3, 1:0. The actual nota-tion used for vectors and subvectors varies among the schematic drawing tools or HDL tools available. Figure 3-8 illustrates just one approach. For a speci!c tool, the documentation should be consulted.

Value !xing, transferring, and inverting have a variety of applications in logic design. Value !xing involves replacing one or more variables with constant values 1 and 0. Value !xing may be permanent or temporary. In permanent value !xing, the value can never be changed. In temporary value !xing, the values can be changed, often by mechanisms somewhat different from those employed in ordi-nary logical operation. A major application of !xed and temporary value !xing is in programmable logic devices. Any logic function that is within the capacity of the programmable device can be implemented by !xing a set of values, as illustrated in the next example.

EXAMPLE 3-4 Lecture-Hall Lighting Control Using Value Fixing

The Problem: The design of a part of the control for the lighting of a lecture hall speci!es that the switches that control the normal lights be programmable. There are to be three different modes of operation for the two switches. Switch P is on the po-dium in the front of the hall and switch R is adjacent to a door at the rear of the

0 F3

1 F2

A F1

A F0

(a)

0

1

A

A

1

2 34

F

0

(b)

4 2:1 F(2:1)2

F(c)

4 3,1:0 F(3), F(1:0)3

F(d)

FIGURE 3-8Implementation of Multibit Rudimentary Functions

M03_MANO0637_05_SE_C03.indd 124 23/01/15 1:51 PM

124 CHAPTER 3 / COMBINATIONAL LOGIC!DESIGN

least signi!cant bit, providing the vector F = (F3, F2, F1, F0). Suppose that F consists of rudimentary functions F3 = 0, F2 = 1, F1 = A, and F0 = A. Then we can write F as the vector (0, 1, A, A). For A = 0, F = (0, 1, 0, 1) and for A = 1, F = (0, 1, 1, 0). This multiple-bit function can be referred to as F(3:0) or simply as F and is imple-mented in Figure 3-8(a). For convenience in schematics, we often represent a set of multiple, related wires by using a single line of greater thickness with a slash, across the line. An integer giving the number of wires represented accompanies the slash as shown in Figure 3-8(b). In order to connect the values 0, 1, X, and X to the appropri-ate bits of F, we break F up into four wires, each labeled with the bit of F. Also, in the process of transferring, we may wish to use only a subset of the elements in F—for example, F2 and F1. The notation for the bits of F can be used for this purpose, as shown in Figure 3-8(c). In Figure 3-8(d), a more complex case illustrates the use of F3, F1, F0 at a destination. Note that since F3, F1, and F0 are not all together, we cannot use the range notation F(3:0) to denote this subvector. Instead, we must use a combi-nation of two subvectors, F(3), F(1:0), denoted by subscripts 3, 1:0. The actual nota-tion used for vectors and subvectors varies among the schematic drawing tools or HDL tools available. Figure 3-8 illustrates just one approach. For a speci!c tool, the documentation should be consulted.

Value !xing, transferring, and inverting have a variety of applications in logic design. Value !xing involves replacing one or more variables with constant values 1 and 0. Value !xing may be permanent or temporary. In permanent value !xing, the value can never be changed. In temporary value !xing, the values can be changed, often by mechanisms somewhat different from those employed in ordi-nary logical operation. A major application of !xed and temporary value !xing is in programmable logic devices. Any logic function that is within the capacity of the programmable device can be implemented by !xing a set of values, as illustrated in the next example.

EXAMPLE 3-4 Lecture-Hall Lighting Control Using Value Fixing

The Problem: The design of a part of the control for the lighting of a lecture hall speci!es that the switches that control the normal lights be programmable. There are to be three different modes of operation for the two switches. Switch P is on the po-dium in the front of the hall and switch R is adjacent to a door at the rear of the

0 F3

1 F2

A F1

A F0

(a)

0

1

A

A

1

2 34

F

0

(b)

4 2:1 F(2:1)2

F(c)

4 3,1:0 F(3), F(1:0)3

F(d)

FIGURE 3-8Implementation of Multibit Rudimentary Functions

M03_MANO0637_05_SE_C03.indd 124 23/01/15 1:51 PM

④ Multiple-bit Function

Dimension

Taking part of the Vector

Concep

t

P1 Elementary Func.124 CHAPTER 3 / COMBINATIONAL LOGIC!DESIGN

least signi!cant bit, providing the vector F = (F3, F2, F1, F0). Suppose that F consists of rudimentary functions F3 = 0, F2 = 1, F1 = A, and F0 = A. Then we can write F as the vector (0, 1, A, A). For A = 0, F = (0, 1, 0, 1) and for A = 1, F = (0, 1, 1, 0). This multiple-bit function can be referred to as F(3:0) or simply as F and is imple-mented in Figure 3-8(a). For convenience in schematics, we often represent a set of multiple, related wires by using a single line of greater thickness with a slash, across the line. An integer giving the number of wires represented accompanies the slash as shown in Figure 3-8(b). In order to connect the values 0, 1, X, and X to the appropri-ate bits of F, we break F up into four wires, each labeled with the bit of F. Also, in the process of transferring, we may wish to use only a subset of the elements in F—for example, F2 and F1. The notation for the bits of F can be used for this purpose, as shown in Figure 3-8(c). In Figure 3-8(d), a more complex case illustrates the use of F3, F1, F0 at a destination. Note that since F3, F1, and F0 are not all together, we cannot use the range notation F(3:0) to denote this subvector. Instead, we must use a combi-nation of two subvectors, F(3), F(1:0), denoted by subscripts 3, 1:0. The actual nota-tion used for vectors and subvectors varies among the schematic drawing tools or HDL tools available. Figure 3-8 illustrates just one approach. For a speci!c tool, the documentation should be consulted.

Value !xing, transferring, and inverting have a variety of applications in logic design. Value !xing involves replacing one or more variables with constant values 1 and 0. Value !xing may be permanent or temporary. In permanent value !xing, the value can never be changed. In temporary value !xing, the values can be changed, often by mechanisms somewhat different from those employed in ordi-nary logical operation. A major application of !xed and temporary value !xing is in programmable logic devices. Any logic function that is within the capacity of the programmable device can be implemented by !xing a set of values, as illustrated in the next example.

EXAMPLE 3-4 Lecture-Hall Lighting Control Using Value Fixing

The Problem: The design of a part of the control for the lighting of a lecture hall speci!es that the switches that control the normal lights be programmable. There are to be three different modes of operation for the two switches. Switch P is on the po-dium in the front of the hall and switch R is adjacent to a door at the rear of the

0 F3

1 F2

A F1

A F0

(a)

0

1

A

A

1

2 34

F

0

(b)

4 2:1 F(2:1)2

F(c)

4 3,1:0 F(3), F(1:0)3

F(d)

FIGURE 3-8Implementation of Multibit Rudimentary Functions

M03_MANO0637_05_SE_C03.indd 124 23/01/15 1:51 PM

④ Multiple-bit Function

124 CHAPTER 3 / COMBINATIONAL LOGIC!DESIGN

least signi!cant bit, providing the vector F = (F3, F2, F1, F0). Suppose that F consists of rudimentary functions F3 = 0, F2 = 1, F1 = A, and F0 = A. Then we can write F as the vector (0, 1, A, A). For A = 0, F = (0, 1, 0, 1) and for A = 1, F = (0, 1, 1, 0). This multiple-bit function can be referred to as F(3:0) or simply as F and is imple-mented in Figure 3-8(a). For convenience in schematics, we often represent a set of multiple, related wires by using a single line of greater thickness with a slash, across the line. An integer giving the number of wires represented accompanies the slash as shown in Figure 3-8(b). In order to connect the values 0, 1, X, and X to the appropri-ate bits of F, we break F up into four wires, each labeled with the bit of F. Also, in the process of transferring, we may wish to use only a subset of the elements in F—for example, F2 and F1. The notation for the bits of F can be used for this purpose, as shown in Figure 3-8(c). In Figure 3-8(d), a more complex case illustrates the use of F3, F1, F0 at a destination. Note that since F3, F1, and F0 are not all together, we cannot use the range notation F(3:0) to denote this subvector. Instead, we must use a combi-nation of two subvectors, F(3), F(1:0), denoted by subscripts 3, 1:0. The actual nota-tion used for vectors and subvectors varies among the schematic drawing tools or HDL tools available. Figure 3-8 illustrates just one approach. For a speci!c tool, the documentation should be consulted.

Value !xing, transferring, and inverting have a variety of applications in logic design. Value !xing involves replacing one or more variables with constant values 1 and 0. Value !xing may be permanent or temporary. In permanent value !xing, the value can never be changed. In temporary value !xing, the values can be changed, often by mechanisms somewhat different from those employed in ordi-nary logical operation. A major application of !xed and temporary value !xing is in programmable logic devices. Any logic function that is within the capacity of the programmable device can be implemented by !xing a set of values, as illustrated in the next example.

EXAMPLE 3-4 Lecture-Hall Lighting Control Using Value Fixing

The Problem: The design of a part of the control for the lighting of a lecture hall speci!es that the switches that control the normal lights be programmable. There are to be three different modes of operation for the two switches. Switch P is on the po-dium in the front of the hall and switch R is adjacent to a door at the rear of the

0 F3

1 F2

A F1

A F0

(a)

0

1

A

A

1

2 34

F

0

(b)

4 2:1 F(2:1)2

F(c)

4 3,1:0 F(3), F(1:0)3

F(d)

FIGURE 3-8Implementation of Multibit Rudimentary Functions

M03_MANO0637_05_SE_C03.indd 124 23/01/15 1:51 PM

Output: (F2, F1)

Output: (F3, F1, F0)

124 CHAPTER 3 / COMBINATIONAL LOGIC!DESIGN

least signi!cant bit, providing the vector F = (F3, F2, F1, F0). Suppose that F consists of rudimentary functions F3 = 0, F2 = 1, F1 = A, and F0 = A. Then we can write F as the vector (0, 1, A, A). For A = 0, F = (0, 1, 0, 1) and for A = 1, F = (0, 1, 1, 0). This multiple-bit function can be referred to as F(3:0) or simply as F and is imple-mented in Figure 3-8(a). For convenience in schematics, we often represent a set of multiple, related wires by using a single line of greater thickness with a slash, across the line. An integer giving the number of wires represented accompanies the slash as shown in Figure 3-8(b). In order to connect the values 0, 1, X, and X to the appropri-ate bits of F, we break F up into four wires, each labeled with the bit of F. Also, in the process of transferring, we may wish to use only a subset of the elements in F—for example, F2 and F1. The notation for the bits of F can be used for this purpose, as shown in Figure 3-8(c). In Figure 3-8(d), a more complex case illustrates the use of F3, F1, F0 at a destination. Note that since F3, F1, and F0 are not all together, we cannot use the range notation F(3:0) to denote this subvector. Instead, we must use a combi-nation of two subvectors, F(3), F(1:0), denoted by subscripts 3, 1:0. The actual nota-tion used for vectors and subvectors varies among the schematic drawing tools or HDL tools available. Figure 3-8 illustrates just one approach. For a speci!c tool, the documentation should be consulted.

Value !xing, transferring, and inverting have a variety of applications in logic design. Value !xing involves replacing one or more variables with constant values 1 and 0. Value !xing may be permanent or temporary. In permanent value !xing, the value can never be changed. In temporary value !xing, the values can be changed, often by mechanisms somewhat different from those employed in ordi-nary logical operation. A major application of !xed and temporary value !xing is in programmable logic devices. Any logic function that is within the capacity of the programmable device can be implemented by !xing a set of values, as illustrated in the next example.

EXAMPLE 3-4 Lecture-Hall Lighting Control Using Value Fixing

The Problem: The design of a part of the control for the lighting of a lecture hall speci!es that the switches that control the normal lights be programmable. There are to be three different modes of operation for the two switches. Switch P is on the po-dium in the front of the hall and switch R is adjacent to a door at the rear of the

0 F3

1 F2

A F1

A F0

(a)

0

1

A

A

1

2 34

F

0

(b)

4 2:1 F(2:1)2

F(c)

4 3,1:0 F(3), F(1:0)3

F(d)

FIGURE 3-8Implementation of Multibit Rudimentary Functions

M03_MANO0637_05_SE_C03.indd 124 23/01/15 1:51 PM

Dimension

Selected Indices

Enabler

Concep

t

P1 Elementary Func.

⑤ Enabler

• Transferring function, but with an additional signal acting as switchEN

EN X F

0 X 0

1 0 0

1 1 1

Enabler

Concep

t

P1 Elementary Func.

⑤ Enabler

• Transferring function, but with an additional signal acting as switchEN

ENX

F ENX

F

Enabler• A building with individual lights , and individual switches

• controls

• Master switch:

F(3 : 0) S(3 : 0)

Si Fi

EN

Example

P1 Elementary Func.

ENS3 F3

F2

F1

F0

S2

S1

S0

Enabler• A building with individual lights , and individual switches

• controls

• Master switch:

F(3 : 0) S(3 : 0)

Si Fi

EN

Example

P1 Elementary Func.

ENS3 3

2

1

0

S2

S1

S0

F4

④ Multiple-bit Function

Summary

① Value-Fixing

② Transferring

③ Inverting

④ Multiple-bit Function

⑤ Enabler

Summary

P1 Elementary Func.

Decoding

Summary

P2 Decoder

-bit input, -bit outputn 2n

Decoder

• -bit input

• different combinations

• Decoder

• -bit input, - outputeach unique input produces a unique output

n

2n

n n 2n

Concep

t

P2 Decoder

1-to-2 Decoder

• 1bit input, 2bits output

Concep

t

P2 Decoder

A D0 D1

0 1 0

1 0 1

A D0 = A

D1 = A

Technology• 1 x NOT Gate

2-to-4 Decoder• 2bit input, 4bits output

• Di = mi

Concep

t

P2 Decoder

A1 A0 D0 D1 D2 D3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

3-5 / Decoding 129

each output. In the logic diagram in Figure 3-13(b), each minterm is implemented by a 2-input AND gate. These AND gates are connected to two 1–to–2-line decoders, one for each of the lines driving the AND gate inputs.

Large decoders can be constructed by simply implementing each minterm function using a single AND gate with more inputs. Unfortunately, as decoders become larger, this approach gives a high gate-input cost. In this section, we give a! procedure that uses design hierarchy and collections of AND gates to con-struct!any decoder with n inputs and 2n outputs. The resulting decoder has the same or a lower gate-input cost than the one constructed by simply enlarging each AND gate.

To construct a 3–to–8-line decoder (n = 3), we can use a 2–to–4-line decoder and a 1–to–2-line decoder feeding eight 2-input AND gates to form the minterms. Hierarchically, the 2–to–4-line decoder can be implemented using two 1–to–2-line decoders feeding four 2-input AND gates, as observed in Figure 3-13. The resulting structure is shown in Figure 3-14.

The general procedure is as follows:

1. Let k = n.

2. If k is even, divide k by 2 to obtain k/2. Use 2k AND gates driven by two decod-ers of output size 2k/2. If k is odd, obtain (k + 1)/2 and (k - 1)/2. Use 2k AND

AD0 ! A

D0

D1 ! A

D1

0 1 01 0 1

(a) (b)

A

FIGURE 3-12A 1–to–2-Line Decoder

A1

0011

A0

0101

D0

1000

D1

0100

D2

0010

D3

0001

(a)

(b)

A

D A1A0

A1A0

A1A0

A1A0D

D

D

1

A0

FIGURE 3-13A 2–to–4-Line Decoder

M03_MANO0637_05_SE_C03.indd 129 23/01/15 1:51 PM

Technology• 2 x NOT Gate• 4 x 2-input AND Gate

2-to-4 Decoder• 2bit input, 4bits output

• Di = mi

Concep

t

P2 Decoder

A1 A0 D0 D1 D2 D3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

3-5 / Decoding 129

each output. In the logic diagram in Figure 3-13(b), each minterm is implemented by a 2-input AND gate. These AND gates are connected to two 1–to–2-line decoders, one for each of the lines driving the AND gate inputs.

Large decoders can be constructed by simply implementing each minterm function using a single AND gate with more inputs. Unfortunately, as decoders become larger, this approach gives a high gate-input cost. In this section, we give a! procedure that uses design hierarchy and collections of AND gates to con-struct!any decoder with n inputs and 2n outputs. The resulting decoder has the same or a lower gate-input cost than the one constructed by simply enlarging each AND gate.

To construct a 3–to–8-line decoder (n = 3), we can use a 2–to–4-line decoder and a 1–to–2-line decoder feeding eight 2-input AND gates to form the minterms. Hierarchically, the 2–to–4-line decoder can be implemented using two 1–to–2-line decoders feeding four 2-input AND gates, as observed in Figure 3-13. The resulting structure is shown in Figure 3-14.

The general procedure is as follows:

1. Let k = n.

2. If k is even, divide k by 2 to obtain k/2. Use 2k AND gates driven by two decod-ers of output size 2k/2. If k is odd, obtain (k + 1)/2 and (k - 1)/2. Use 2k AND

AD0 ! A

D0

D1 ! A

D1

0 1 01 0 1

(a) (b)

A

FIGURE 3-12A 1–to–2-Line Decoder

A1

0011

A0

0101

D0

1000

D1

0100

D2

0010

D3

0001

(a)

(b)

A

D A1A0

A1A0

A1A0

A1A0D

D

D

1

A0

FIGURE 3-13A 2–to–4-Line Decoder

M03_MANO0637_05_SE_C03.indd 129 23/01/15 1:51 PM

Technology• 2 x NOT Gate• 4 x 2-input AND Gate

2-to-4 Decoder• 2bit input, 4bits output

• Di = mi

Concep

t

P2 Decoder

A1 A0 D0 D1 D2 D3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

A0

A1

D0 = A1A0

D1 = A1A0

D2 = A1A0

D3 = A1A0

Technology• 2 x 1-to-2 Decoder• 4 x 2-input AND Gate

3-to-8 Decoder• 3bit input, 8bits output

• Di = mi

Concep

t

P2 Decoder

A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

Technology• 1 x 1-to-2 Decoder• 1 x 2-to-4 Decoder• 8 x 2-input AND Gate

3-to-8 Decoder• 3bit input, 8bits output

• Di = mi

Concep

t

P2 Decoder

A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

Technology• 1 x 1-to-2 Decoder• 1 x 2-to-4 Decoder• 8 x 2-input AND Gate

3-to-8 Decoder• 3bit input, 8bits output

• Di = mi

Concep

t

P2 Decoder

A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7

0

0 0 1 0 0 0 0 0 0 00 1 0 1 0 0 0 0 0 01 0 0 0 1 0 0 0 0 01 1 0 0 0 1 0 0 0 0

1

0 0 0 0 0 0 1 0 0 00 1 0 0 0 0 0 1 0 01 0 0 0 0 0 0 0 1 01 1 0 0 0 0 0 0 0 1

Technology• 1 x 1-to-2 Decoder• 1 x 2-to-4 Decoder• 8 x 2-input AND Gate

A0

A1

A2

2-to-4 Decoder

D33 = A2D2

3

D32 = A2D2

2

D31 = A2D2

1

D30 = A2D2

0

D37 = A2D2

3

D36 = A2D2

2

D35 = A2D2

1

D34 = A2D2

0

1-to-2 Decoder

3-to-8 Decoder• 3bit input, 8bits output

• Di = mi

Concep

t

P2 Decoder

A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7

0

0 0 1 0 0 0 0 0 0 00 1 0 1 0 0 0 0 0 01 0 0 0 1 0 0 0 0 01 1 0 0 0 1 0 0 0 0

1

0 0 0 0 0 0 1 0 0 00 1 0 0 0 0 0 1 0 01 0 0 0 0 0 0 0 1 01 1 0 0 0 0 0 0 0 1

Technology• 1 x 1-to-2 Decoder• 1 x 2-to-4 Decoder• 8 x 2-input AND Gate

A0

A1

A2

2-to-4 Decoder

1-to-2 Decoder

D33 = A2D2

3

D32 = A2D2

2

D31 = A2D2

1

D30 = A2D2

0

D37 = A2D2

3

D36 = A2D2

2

D35 = A2D2

1

D34 = A2D2

0

Incremental Design

4-to-16 Decoder• 4bit input, 16bits output

• Di = mi

Concep

t

P2 Decoder

1. Incomplete Truth table

A3 A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7

0

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

Technology• 1 x 1-to-2 Decoder• 1 x 3-to-8 Decoder• 16 x 2-input AND Gate

A3 A2 A1 A0 D8 D9 D10 D11 D12 D13 D14 D15

1

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

Incremental Design

D40:7 = A3D3

0:7 D48:15 = A3D3

0:7

4-to-16 Decoder• 4bit input, 16bits output

• Di = mi

Concep

t

P2 Decoder

Technology• 1 x 1-to-2 Decoder• 1 x 3-to-8 Decoder• 16 x 2-input AND Gate

Incremental Design

A0

A1A2

3-to-8 Decoder

A3 1-to-2 Decoder

16 x 2-input AND Gates

…

…

D40:7 = A3D3

0:7

D48:15 = A3D3

0:7

4-to-16 Decoder• 4bit input, 16bits output

• Di = mi

Concep

t

P2 Decoder

1. Incomplete Truth table

A3 A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7

0

0

0 0 1 0 0 0 0 0 0 00 1 0 1 0 0 0 0 0 01 0 0 0 1 0 0 0 0 01 1 0 0 0 1 0 0 0 0

1

0 0 0 0 0 0 1 0 0 00 1 0 0 0 0 0 1 0 01 0 0 0 0 0 0 0 1 01 1 0 0 0 0 0 0 0 1

Technology• 2 x 2-to-4 Decoder• 16 x 2-input AND Gate

A3 A2 A1 A0 D8 D9 D10 D11 D12 D13 D14 D15

1

0

0 0 1 0 0 0 0 0 0 00 1 0 1 0 0 0 0 0 01 0 0 0 1 0 0 0 0 01 1 0 0 0 1 0 0 0 0

1

0 0 0 0 0 0 1 0 0 00 1 0 0 0 0 0 1 0 01 0 0 0 0 0 0 0 1 01 1 0 0 0 0 0 0 0 1

Recursive Design

D40:7 = A3D3

0:7 D48:15 = A3D3

0:7

4-to-16 Decoder• 4bit input, 16bits output

• Di = mi

Concep

t

P2 Decoder

1. Incomplete Truth table

Technology• 2 x 2-to-4 Decoder• 16 x 2-input AND GateRecursive Design

D40:7 = A3D3

0:7 D48:15 = A3D3

0:7

2-to-4 Decoder

2-to-4 Decoder

16 x 2-input AND Gates

…

A0

A1

A2

A3

D40:3 = A3A2D2

D44:7 = A3A2D2

D48:11 = A3A2D2

D412:15 = A3A2D2

4-to-16 Decoder• 4bit input, 16bits output

• Di = mi

Concep

t

P2 Decoder

Technology• 2 x 2-to-4 Decoder• 16 x 2-input AND GateRecursive Design

D40:7 = A3D3

0:7

D48:15 = A3D3

0:7

4-to-16 Decoder• 4bit input, 16bits output

• Di = mi

Concep

t

P2 Decoder

Technology• 2 x 2-to-4 Decoder• 16 x 2-input AND GateRecursive Design

D4 = D40:15 = [A3D3

0:7; A3D30:7] = [A3D3; A3D3]

Bracket: concatenation of vectors

4-to-16 Decoder• 4bit input, 16bits output

• Di = mi

Concep

t

P2 Decoder

Technology• 2 x 2-to-4 Decoder• 16 x 2-input AND GateRecursive Design

D4 = [A3D3; A3D3]

4-to-16 Decoder• 4bit input, 16bits output

• Di = mi

Concep

t

P2 Decoder

Technology• 2 x 2-to-4 Decoder• 16 x 2-input AND GateRecursive Design

D3 = [

A2D20

A2D21

A2D22

A2D23

;

A2D20

A2D21

A2D22

A2D23

] = [A2

D20

D21

D22

D23

; A2

D20

D21

D22

D23

] = [A2D2; A2D2]

D4 = [A3D3; A3D3]

4-to-16 Decoder• 4bit input, 16bits output

• Di = mi

Concep

t

P2 Decoder

Technology• 2 x 2-to-4 Decoder• 16 x 2-input AND GateRecursive Design

D4 = [A3D3; A3D3]

D3 = [A2D2; A2D2]

4-to-16 Decoder• 4bit input, 16bits output

• Di = mi

Concep

t

P2 Decoder

Technology• 2 x 2-to-4 Decoder• 16 x 2-input AND GateRecursive Design

D4 = [A3D3; A3D3]D3 = [A2D2; A2D2]

= [A3[A2D2; A2D2]; A3[A2D2; A2D2]]= [A3A2D2; A3A2D2]; [A3A2D2; A3A2D2]]= [A3A2D2; A3A2D2; A3A2D2; A3A2D2]= [A3A2; A3A2; A3A2; A3A2]D2

Summary

• What is a decoder

• Truth table of a decoder

• Implementation of 1-to-2, 2-to-4, -to- decoder

• Incremental design

• Recursive design

n 2n

Summary

P2 Decoder

1-bit Binary Adder

Summary

P3 Example 3d

Using decoder

Binary Addition

Review

P3 Example 3d

1101001101

+0010110010

Augend X

Carries Z

Addend Y

Sum

1-bit Binary Adder• Binary Adder

• Logical functional block that performs addition

• 1-Bit Binary Adder: smallest building block of a multi-bit adder

• InputsAugend: ; Addend: ; Previous Carry:

• OutputsSum bit: ; next carry:

X Y Z

S C

Concep

t

P3 Example 3d

1. Specification

Example

P3 Example 3d

ZX

+YAugend

Carries

Addend

Sum S

C

+

InputOutputX

YZ

1-Bit Binary Adder

S

C

SC

2. FormulationP3

Example 3d

ZX

+YAugend

Carries

Addend

Sum S

C

+

InputOutput

X Y Z S C

0 0 00 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Example

2. FormulationP3

Example 3d

ZX

+YAugend

Carries

Addend

Sum S

C

+

InputOutput

X Y Z C S

0 0 0 0 0

0 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

Example

2. FormulationP3

Example 3d

ZX

+YAugend

Carries

Addend

Sum S

C

+

InputOutput

X Y Z C S

0 0 0 0 0

0 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

Example

Sum of Minterms

C = Σm(3,5,6,7)

S = Σm(1,2,4,7)

3. OptimisationP3

Example 3d

ZX

+YAugend

Carries

Addend

Sum S

C

+

InputOutput

X Y Z C S

0 0 0 0 0

0 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

Example

Sum of Minterms

C = Σm(3,5,6,7)

S = Σm(1,2,4,7)

We can use decoders to implement the adder!

3. OptimisationP3

Example 3d

ZX

+YAugend

Carries

Addend

Sum S

C

+

InputOutput

X Y Z C S

0 0 0 0 0

0 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

Example

Sum of Minterms

C = Σm(3,5,6,7)

S = Σm(1,2,4,7)

We can use decoders to implement the adder!

4. Technology MappingP3

Example 3d

Example

Sum of Minterms

C = Σm(3,5,6,7)

S = Σm(1,2,4,7)

Technology• 1 x 3-to-8 Decoder• OR Gates

XYZ

3-to-8 Decoder

01234567

0

1

2 C

S