03

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 4, APRIL 2013 1655

Grid-Interface Bidirectional Converter for ResidentialDC Distribution Systems—Part One: High-Density

Two-Stage TopologyDong Dong, Student Member, IEEE, Igor Cvetkovic, Student Member, IEEE, Dushan Boroyevich, Fellow, IEEE,

Wei Zhang, Student Member, IEEE, Ruxi Wang, Student Member, IEEE, and Paolo Mattavelli, Senior Member, IEEE

Abstract—With the emerging installations of multitype renew-able energy sources and energy storage elements, the dc electronicdistribution systems in residential buildings (dc nanogrid) are be-coming an alternative future system solution, achieving a zero net-energy consumption and optimized power management. The con-cept of the energy control center (ECC), which interconnects thedc system to the traditional ac utility grid, is introduced, and theoperation function of ECC converter suitable for dc nanogrid ap-plication is defined. This paper investigates a two-stage topologyusing a full bridge in series with a bidirectional synchronous recti-fier dc–dc converter as a single-phase ECC for dc nanogrid, with asignificant reduction of the dc-link capacitor value. The operationanalysis and the design of passive components are provided. A bidi-rectional control system and the design process are also presentedin terms of the system requirement and the small dc-link capacitor.

Index Terms—DC distribution, renewable energy, single phase.

I. INTRODUCTION OF THE DC NANOGRID

AND ECC CONVERTER

IN conventional electric power systems, generation and con-sumption are fully coupled through the overwhelmingly slow

dynamics of the electromechanically anchored constant fre-quency of the rotating masses, assuring transient, and staticstability. Guaranteed delivery of energy to the consumers isonly ensured through redundancy, overdesign, and electrome-chanically controlled system reconfigurations, which added tothe fact that grid infrastructure is aging, inevitably leads to theconclusion that existing power system can be considered to beinherently slow, inefficient, and more and more unreliable [1].

The power generation, transmission, and distribution facil-ities cannot easily respond to the variable dynamics of thedistributed-generation-sources (DGS), fast load changes, andmore high-frequency oscillations, thus degrading the reliabil-ity and stability of the power system [2], [3]. Additionally, itsmaintenance cost is constantly increasing since the mechanicalequipment tends to wear out more quickly than the static elec-tronic devices, greatly influencing overall system efficiency [7].

Manuscript received April 9, 2012; revised June 19, 2012; accepted July 23,2012. Date of current version October 26, 2012. Recommended for publicationby Associate Editor V. Staudt.

The authors are with the Center for Power Electronics Systems (CPES),Virginia Tech, Blacksburg, VA 24061 USA (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2012.2212462

Moreover, in the way it is built today, the traditional radial ar-chitecture and unidirectional feeder protection cannot easily, orwithout some significant changes, accept high penetration ofDGS and renewable energy sources (RES).

Higher engagement of power electronics converters with theembedded advanced control into the power system structureoffers encouraging solutions to many of the issues mentionedearlier [1]–[6]. The intermittent dynamics of the RES can nowbe decoupled by power electronics to avoid transient stabilityproblems [2], [4] and to provide the control of active/reactivepower for the system voltage support and frequency stabiliza-tion. Adoption of power electronics loads, such as variable speeddrives in industries, electronic loads in commercial environment,and smart appliances in residential buildings, not only increasethe energy efficiency, but also provide the smart metering [4]by instantaneously recording the system states and parameters,which at the end can be used by power system operators andplanners for demand-response operation. In addition to this,power electronics source/loads can provide fast fault detectionand protection, thereby possibly significantly reducing the needfor mechanical breakers [3]–[5].

Beside the more engagement of power electronics source andpower electronic loads, it may not be impossible that the fu-ture electric power distribution systems backbone will be alsobased on power electronic converters taking the role of en-ergy control centers (ECC), like an “energy router,” used tointerconnect several subsystems, such as the micro-, mini- andnanogrid [4], [8], [9]. As a result, the dynamics interactions andfaults of interconnected systems, such as synchronizations, out-ages, and blackouts, will be decoupled and isolated from eachother, effectively preventing the cascading system failure. In ad-dition, the complexity of the overall system can be degraded,due in large to the decoupling of operation, thereby reducingthe effort needed for system-level design and integration. Thewhole system will be more controllable and autonomous, like-wise smarter.

The basic functions of such ac–ac or ac–dc ECCs for thefuture more-electronic power distribution system would be [4]:1) bidirectional power flow operation; 2) dynamics decouplingof interfaced systems; 3) bidirectional fault current interruptcapability; and 4) smart metering and communication functions.

As shown in Fig. 1, a single-phase ac–dc ECC and a dcelectronic distribution system, i.e., dc nanogird, in homeenvironment can be studied as a specific example of futuremore-electronic electric power system. DC is a straightforward

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1656 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 4, APRIL 2013

Fig. 1. Structure of dc nanogrid in home.

and simple solution [4], [8], [10]–[13] to integrate multiplesources and loads, such as PV cells, energy storage devices,variable-speed motor drives in appliances, and solid-statelightings, as there are no ac losses, no reactive power issues,and frequency synchronization issues [14], [15]. Since nowmost of the household appliances are electronic loads, the dcsystem also helps eliminate the power-factor-correction (PFC)stages in appliances.

Multiple distributed renewable energy resources, energy stor-age elements and loads are connected to a 380-V dc nanogridsystem through different power converters [4], as illustratedin Fig. 1. Another low-voltage 24 or 48-V dc bus is forthe consumer electronic devices and portable equipment. Assuch, all the sources and loads form an “electronic-based” dcnanogrid, which is fully dynamically decoupled from the grid.DC nanogrid is self-sustainable by its own dc sources and a zeronet-energy consumption of house is possible. The current-limitprotection functions are built in every converter, achieving thebreakerless system architecture. This proposed dc nanogrid isunlike of the current dc distribution system solution in data cen-ter, in which battery is directly tied to the dc bus for voltageregulation purpose [16].

The ECC converter allows the power demand/response oper-ation with utility, and specifically, aside from ac current regula-tion, regulates the dc system bus voltage (around 380 V) withfast dynamics and a small ripple. Several major characteristics ofthis ECC converter include but are not limited to the following:

1) DC-bus high-voltage (around 380 V) stiff and fast regu-lation with the droop characteristics [4], [17]: the ECCcan ride-through the transient dynamics happened on bothac and dc sides, achieving the decoupled operation. Thedroop characteristics help attain the current sharing be-tween multiple sources.

2) Taut regulation of ac current: it operates to comply withthe utility-interface codes [18], thus the whole dc system

Fig. 2. ECC converter dc-side output V–I operation curve.

behaves like a simple ac load/source. As such, the dcdynamics will be transparent to the utility side.

3) Bidirectional-oriented topology: it provides the dc systemthe opportunity to regenerate the power back to the utility,so the ECC is more like an energy router, giving moreoptions to residents for power management.

4) Bidirectional fault current interrupting capability: the cur-rent limit protection is integrated into the power converteritself, eliminating the need for bulky and expensive me-chanical protection devices, e.g., circuit breaker, on bothsides.

5) Small-stored static energy on dc side: it can reduce thetransient energy spike under the shot-circuit condition,thus reducing the safety challenge to human.

6) High power density, high efficiency, and low cost.

II. IMPACT OF RIPPLE POWER ON DC NANOGRID

Other than the power conversion functionality, the topologyselection of the ECC converter depends much on the applicationsrequirements, electrical system practices, grounding scheme,system-level protection and EMI, etc. The topology candidatestypically can be categorized into isolated and transformerlesstopologies. The isolated topology provides the feasibility ofsystem grounding solutions. However, high-frequency isolationtopology normally requires more conversion stages, more de-vices which reduce the efficiency and reliability, and the line-frequency isolation significantly increases the overall systemfootprint as well as reduces the efficiency. In residential ap-plication (10–100 kW), transformerless topology is more costeffective, more efficient and reliable.

The bus-signaling technique [4], [16], [19], [20] by using thedroop control accomplishes the current sharing independent ofthe communication among converters on dc side. The nominalvoltage of the dc-bus is 380 V, but the operating voltage of thedc bus is chosen to be in a range, e.g., between 360 and 400 V, toallow for power sharing and voltage regulation using the droopcontrol. The static V–I curve of ECC is shown in Fig. 2 [4] whereRd is the droop value. In the first quadrant of the V–I plane ECCis taking energy from the grid when the dc output current Ig ispositive, while in the second quadrant it is sourcing energy backto the grid.

If the ECC output is overloaded or even shorted in the firstquadrant, the ECC limits the output current to IgD in Fig. 2. Ifthe operator of the utility to which the nanogrid is connected

DONG et al.: GRID-INTERFACE BIDIRECTIONAL CONVERTER FOR RESIDENTIAL DC DISTRIBUTION SYSTEMS—PART ONE 1657

Fig. 3. Single-phase full-bridge converter.

requests from the ECC a specific amount of power that is lessthan the converter rating, the converter can reprogram its V–Icharacteristic in the second quadrant to limit the current to avalue that corresponds to the demanded power, as representedby the dotted line. Under these two conditions, the battery on thedc-side can take charge of the dc-bus voltage regulation via thebidirectional charger (BDC) [11]. The current-limit function es-sentially can reduce the use of additional mechanical protectiondevices.

The full-bridge topology, as shown in Fig. 3, is widely used asa bidirectional topology for energy delivery between the ac gridand dc RES/system [10], [14], [15], [21] which processes theenergy either in rectification mode (ac to dc), or in regenerationmode (dc to ac) [15], [22].

As shown in Fig. 3, the grid current and voltage are definedin (1) and (2), in which the power factor (PF) angle is ϕ

iac = Is sin (ωot − ϕ) (1)

uac = Us sin(ωot). (2)

The power Pin that flows through the full-bridge topologywill be the full-bridge terminal voltage vab multiplied by inputcurrent iac , as shown in (3). The voltage difference between vaband input voltage uac is the voltage across the ac inductor Lac ,as shown in (4)

Pin = vab · iac (3)

vab = Us sin (ωot) − ωoLacIs cos (ωot − ϕ) . (4)

Pin consists of two parts: the dc average power Pav in (5),and the second-order ripple power Pr in (6)

Pav =UsIs

2cos ϕ (5)

Pr = −UsIs

2cos(2ωot − ϕ) − ωoLacI

2s

2sin(2ωot − 2ϕ)

=

√P 2

av +(

ωoLacI2s

2−Pav

sinϕ

cos ϕ

)2

sin(2ωot−2ϕ + ψ),

ψ = arctanPav

ωo La c I 2s

2 − Pavsin ϕcos ϕ

= A sin(2ωot−2ϕ + ψ), ψ=arctanPav

ωo La c I 2s

2 −Pavsin ϕcos ϕ

.

(6)

If the full-bridge topology directly feeds to the dc system, asshown in Fig. 3, which includes a resistor load Ro . Ps is the netpower delivered by other dc sources. The resistor load consumesall the active power under Vo = 380 V, as shown in (7). Then,the equation of (8) is obtained

Ro =V 2

o

Pav + Ps(7)

v2o

Ro+ vo · C

dvo

dt= A sin(2ωot − 2ϕ + ψ) + Pav + Ps. (8)

The differential equation has only one steady-state solutionobtained as follows, as shown (9) at the bottom of the page.

Then, the dc-link voltage ripple can be obtained shown asfollows:

Δvo pp = vo max − vo min

=A

(vo m a x +vo m in )2

√(Pav + Ps/V 2

o )2 + (ωoCdc)2.

(10)

It is seen that the maximum dc-bus voltage ripple under thesame ac input condition occurs when Ps = 0. If the approxima-tion of the average dc-bus voltage is obtained in (11), (10) canbe simplified as (12)

Vo av =1T

∫ t+T

t

vo · dt ≈ vo min + vo max

2(11)

Δvo pp =A

Vo av

√(Pav +Ps

V 2o

)2+ (ωoCdc)2

. (12)

Due to the droop operation range, it is desired to have a smalldc-bus voltage ripple. Specifically, the dc-link capacitors Cdcmust be 6.9 mF based on the specifications in Table I.

Lots of electrolytic capacitors have to be employed as the dc-link capacitor Cdc for single-phase power conversion [14], [15]in the wake of stabilizing the dc-bus voltage. However, the im-pact of ripple power on the dc nanogrid still remains. Whenthe ECC converter operates as a current source or current limitmode and the battery regulates the dc-bus voltage via BDC, theoutput impedance of BDC is determined by the droop resistance,which could be much smaller than the impedance of the dc-buscapacitor at 120 Hz. Thus, as shown in Fig. 4, lots of ripple

vo =

√V 2

o +A√

(Pav + Ps/V 2o )2 + (ωoCdc)2

sin(2ωot − 2ϕ + ψ + λ), λ = − arctan(CdcV2o /Pav + Ps) (9)


TABLE IOPERATIONS SPECIFICATIONS FOR THE FULL-BRIDGE TOPOLOGY FOR DC NANOGRID

Fig. 4. Bidirectional charger (BDC) regulates dc-bus voltage and ECC oper-ates as current limit mode.

Fig. 5. Two-stage bidirectional topology with dc-link capacitor reduction.

power Pr will circulate between the battery and grid, degradingthe battery life time and resulting in more losses. Moreover, thelife-time and power-density of the full-bridge are degraded dra-matically due to the bulky electrolytic capacitors and the safetyissue exists simply because of the large static energy stored inthe dc-link capacitors. Also, full-bridge topology suffers froma shortage of internal active current-limit protection on dc side.Therefore, single-stage topology, such as full bridge, is unableto fulfill the decoupled operation requirement of ECC.

III. HIGH DENSITY TWO-STAGE ECC CONVERTER

FOR DC NANOGRID

In this paper, a two-stage single-phase PWM converter, asshown in Fig. 5, is investigated as the high power-density ECCconverter for such a dc nanogrid application. Two phase-legs areused as the full bridge to interface with the grid. The other phaseleg is used as a bidirectional SR dc–dc converter to regulate thedc-bus voltage with a small voltage ripple and with a fast dy-namic response. Short-circuit protection can be readily attainedin either direction by turning OFF the second-stage or full-bridgeswitches. The black start is simple due to the “buck-type” topol-ogy on both sides. Moreover, in terms of dc system-level designand study of dc-bus converters’ interactions, the second-stagedc–dc converter is deemed advantageous over the dc link of thefull bridge to interface to the dc system. In order to improvethe power density and eliminate the electrolytic capacitors, it isdesirable to analyze the opportunity to shrink the size of dc-linkcapacitor Cdc .

The literature on the single-phase ac–dc converter with re-duced dc-link capacitor volume, which leads to high powerdensity, can be found in [23]–[29]. In [23] and [24], an ad-ditional paralleled phase-leg and an inductor as an auxiliarycircuit to reduce the dc-link voltage ripple is used. Alterna-tively, in [25]–[27], a similar structure but with a capacitor asthe energy storage element is used. An additional ripple energystorage circuit was proposed on the ac line in [28] and in paral-lel with the PFC circuit in [29] to reduce the dc-side capacitorvalue. The drawbacks of the aforementioned approaches are thedifficulty of designing linear-type controls and the sensitivity tosystem parameters. Bidirectional controls and the seamless bidi-rectional mode transition for those topologies have not been welldocumented. In [30] and [31], a dc–dc converter plus silicon-controlled rectifier (SCR) topology is proposed, in which theSCR is switched at line-frequency, leading to low switchingloss . It is seen that existing solutions require additional phaselegs or significant change of topology as well as the need of asophisticated controller, which dramatically reduce the systemreliability and efficiency. Thus, the following analysis tends toaddress the possibility and the corresponding design issue tohighly reduce the dc-link capacitor using the two-stage ECCconverter without additional modifications.

As shown in Fig. 5, the reduction of the dc-link capacitor Cdcwill naturally yield a large dc-link voltage variation. For theconverter to operate using the aforementioned specifications inTable I, two requirements must be fulfilled. First, if the dc-busvoltage Vo is regulated with a very small ripple, the input powerPin should be fully controlled so that all the dc average powerPav flows through the second-stage dc–dc converter and theripple power Pr goes to the small dc-link capacitor Cdc . Second,the input current for this case can still be well controlled as asinusoidal waveform at PF angle ϕ.

If neglecting the instantaneous power PL dissipated on theboost inductor Lac , the first requirement can be expressed in (10)that the instantaneous power Pcap in the dc-link capacitor is thesame as the input ripple power, which is Pr on the right-handside shown as follows:

Pcap = vdc · ic = −UsIs

2cos(2ωot − ϕ) ⇔ Cdc

dvdc

dt

· vdc = −UsIs

2cos(2ωot − ϕ). (13)

By solving the differential equation of (13), the dc-link volt-age vdc can be resolved as in (14); the maximum and minimumdc-link voltages are also shown below in (15). The constantvalue Kc const represents the energy stored in the dc-link ca-pacitor

vdc =√

Kc const −UsIs

2Cdcωosin(2ωot − ϕ) (14)


Fig. 6. Average current ic flowing to Cdc under different Cdc .

vdc min =√

Kc const −UsIs

2Cdcωo

vdc max =√

Kc const +UsIs

2Cdcωo. (15)

The definition of average dc-link voltage Vav is shown in (16).The relationship between Kc const and Vav is then establishedbelow in (17)

Vav =1T

∫ t+T

t

vdc · dt ≈ vdc min + vdc max

2(16)

Kc const = V 2av +

(UsIs

4VavCdcωo

)2

. (17)

The dc-link voltage vdc thereby can be reformed shown asfollows:

vdc =

√(Vav +

UsIs

4VavCdcωo

)2

− UsIs

2Cdcωo[1 + sin(2ωot − ϕ)].

(18)

For any Cdc value, the expression under the radical sign in(18) is larger than zero, offering the possibility of reducing Cdc .Based on (18), the averaged dc-link capacitor current ic andthe averaged current flowing to the dc–dc converter id can bederived as follows:

ic =−Us Is

2 cos (2ωot − ϕ)√(Vav + Us Is

4Vav Cd c ωo

)2− Us Is

2Cd c ωo[1 + sin (2ωot − ϕ)]

(19)

id =Us Is

2 cos ϕ√(Vav + Us Is

4Vav Cd c ωo

)2− Us Is

2Cd c ωo[1 + sin (2ωot − ϕ)]

.

(20)

By assuming the dc-link average voltage is 550 V and theaverage power is 10 kW, ic is shown in Fig. 6 under the differentdc-link capacitor values. This figure shows that the reductionof dc-link capacitor Cdc does not increase the dc-link capacitoraverage current rating. ic under the different dc-link averagevoltage levels Vav with 300 μF Cdc are shown in Fig. 7. It

Fig. 7. Average current flowing to Cdc under different Vav .

shows that the reduction of Vav results in the bigger ic . It isquite evident from Figs. 6 and 7 that the average dc-link voltagelevel has more impact on the current rating of dc-link capacitorthan the value of dc-link capacitor does.

For the ac current regulation requirement, it should be notedthat the dc-link current ichop is the switching current with therectified sinusoidal profile. The average value of ichop should beconfined within the profile of ac current iac such that the secondrequirement can be written as (21). Substituting (19) and (20)into (21) gives (22)

|id + ic | = |ichop | < |Is sin(ωot − ϕ)| (21)

Us < vdc . (22)

Equation (22) indicates that as long as the input grid peakvoltage Us is smaller than the dc-link voltage vdc , ac currentcan be regulated as the sinusoidal waveform regardless of thedc-link capacitor value. Thus, the low-frequency average andripple power can be decoupled with a small Cdc as long as awell-designed controller.

The high-frequency interactions between ac and dc-sidewith a small Cdc can be investigated by comparing the inputimpedance of the second-stage Zin and the impedance of dc-link capacitor ZC dc . Zin at high frequency can be derived as(23), where D is the duty-cycle of the second stage. The impactof the dc-system impedance is ignored as it is decoupled by thelarge capacitance Co , and the Zin is dominated by Lo

Zin =1

D2

s2LoRoCo + sLo + Ro

1 + sRoCo. (23)

The impedance comparisons in high-frequency range(>1 kHz) under different values of Cdc are shown in Fig. 8.It shows that the Zin (components’ values are from Table II)is always higher than ZC dc . As such, all the high-frequencynoises ihs from the grid are routed to Cdc , though very small,achieving the high-frequency dynamics decoupling between dcand ac-sides, as shown in Fig. 9.

Thus, it is appropriate to use the dc–dc converter regulatingthe dc bus voltage Vo with a small ripple plus the full-bridgeregulating ac current with a small dc-link capacitor Cdc . For thiscase, the design of this small Cdc lies in the tradeoff between thepower level Pav , the average dc-link voltage Vav , and the dc-linkvoltage variation range. For a 10-kW average power level, the


TABLE IIMAIN VOLUME COMPARISON BETWEEN TWO-STAGE TOPOLOGY AND H-BRIDGE WHERE fs = 20 KHZ

Fig. 8. Input impedance of second stage Zin and impedance of Cdc under1.1 mF and 200 μF cases.

Fig. 9. Routes of ac-side high-frequency noise ihs .

relationship between the dc-link maximum and minimum values(vdc max , vdc min ), the dc-link voltage average value Vav , andthe dc-link capacitor value Cdc is shown in Fig. 10.

In order to find the minimum dc-link capacitor, the minimumdc-link voltage Vmin value is set as 450 V as the output voltageVo (dc-bus voltage) is controlled at 380 V, and the maximumdc-link voltage value Vmax is set as 650 V. From (14) to (18),the boundary of dc-link capacitor is obtained as follows:

UsIs

4 (Vav − Vmin) Vavωo≤ Cdc ≤

UsIs

4 (Vmax − Vav) Vavωo.

(24)The dc-link capacitor selection range based on (24) can be

readily found in Fig. 11, where the minimum capacitor valuecan be directly found. And the minimum dc-link capacitor valueis derived as follows:

Cdc min =UsIs

(V 2max − V 2

min) ωo. (25)

Fig. 10. vdc m ax and vdc m in in relationship with Cdc and Vav .

Fig. 11. Minimum point of the dc-link capacitor Cdc .

As a result, the minimum capacitor value is observed to be241 μF. In the real system development, to leave a margin, thevalue is chosen as 360 μF. Compared to 6.9 mF, there is ahuge reduction in the dc-link capacitor. The reduction of dc-link capacitor Cdc in turn poses challenges to designing thecontroller to separate the ripple power and dc average power,which is examined in the following section.


Fig. 12. Proposed bidirectional control structure.

IV. BIDIRECTIONAL CONTROL SYSTEM

The proposed bidirectional digital control structure consistsof two independent controllers given in Fig. 12, where other dcrenewable energy resources are simply modeled as the currentsources.

Essentially, one controller is used to control the dc bus voltageVo by operating the dc–dc converter in the SR buck mode or SRboost mode, relying on the power flow direction. The carefullydesigned compensator Hov plus the resonant controller Rovare used to accomplish a high bandwidth and high loop gain,especially at double-line frequency (120 Hz), to handle a largeinput Vdc variation as well as to regulate the output voltage Vo .Hio is used to regulate the dc inductor current and to dampthe resonance formed by the output LC filter. The other double-loop controller controls the full-bridge topology. The outer-loopcontrols the dc-link average voltage Vdc in conjunction with anadditional load current feedback term G, while the inner-loopregulates the power from the grid. The outer-loop controller hasa notch-filter N in series with compensator Hv to correct thecontrol-signal, minimizing the THD of the ac current.

The control delay due to the sensor filter and digital compu-tation must be modeled. Each sensor filter Hfilter is assumed tobe a second-order low-pass-filter. Hdelay is the total delay fromthe controller. GPWM is the PWM modulator gain.

The quasi-static modeling approach [32], [33], due to thevarying line voltage, can be applied to obtain the small-signalcontrol-to-current transfer function of the full-bridge in the high-frequency range in (26), in which dab (between −1 and 1)is the average duty-cycle signal of the full bridge. The inputimpedance of the second-stage converter Zin will be the loadingimpedance to the first stage

Gid =iac

dab= Vdc

2 + sZinCdc

d2abZin + sLac + s2ZinLacCdc

. (26)

Normally, the control bandwidth of Vo is lower than that ofthe ac current loop. So in the high-frequency range around thecross-over frequency of the ac current loop Zin as shown in (23),would be the unregulated input impedance of the second-stageconverter. As such, Hi can be designed to compensate Gid toachieve the high bandwidth and desired phase-margin based on(26).

It is also seen that the ac current loop dynamics after theresonance frequency (Lac , Cdc) will be mostly dominated bythe ac boost inductor Lac , and (27) can be simplified shownfollows:

G′id =

iac

dab= Vdc

1sLac

. (27)

Since the designed bandwidth of dc-link voltage loop is notbeyond the double line-frequency (120 Hz), the inner high band-width ac current loop can be assumed ideal to design the voltagecompensator Hv and the second-stage is regarded as a con-stant power load (CPL). Then, the current-to-dc-link-voltagesmall-signal model in the low-frequency range is obtained in(28) [32], [34]. h is the scaling factor of the PLL

Giv =vdc

vc=

V 2acRMS

hVdc

1sCdc

. (28)

The variable G shown in (29) is applied to balance the powerbetween the dc load and the ac grid, and also to improve the dc-link voltage regulation transient response speed especially dur-ing the load-step period. VacRMS denotes the grid voltage RMSvalue and Vdc ref is the dc-link voltage reference, and HLPF is alow-pass-filer to reduce the sensitivity to high-frequency noise

G(s) =√

2Vdc ref

VacRMS· HLPF(s). (29)

To design the second-stage voltage loop controller, the small-signal models of the second-stage converter can be derived.


The dc loading impedance as well as the small-signal transferfunctions vary with the dc-bus operation. However, in order todesign a fixed compensator, the small-signal model under lightresistor load Ro can be used as the worst case.

The control-to-output inductor current transfer function in(30) is used to design current compensator Hio , and the inductor-to-output voltage transfer function in (31) is used to design theoutput voltage compensator Hvo

Giod =io

d= Vdc

1 + sRoCo

Ro + sLo + s2LoCoRo(30)

Gvoi =vo

io=

Ro

1 + sCoRo. (31)

The droop resistance Rd is included in the dc bus voltageloop to change the ECC converter static dc output impedance.The gain “A” in Fig. 12 is an antiwindup feedback to preventthe voltage-loop controller from saturation when ECC operatesin current limit mode. A detailed compensator design procedurecan be found in [32].

Several more control techniques must be implemented to ef-fectively separate the dc average power and ripple power intotwo paths with a small dc-link capacitor. During the full loadconditions, the dc-link voltage will bear a big 120-Hz ripple vari-ation, which affects the output voltage Vo through the closed-loop audio susceptibility transfer function due to the finite loop-gain at 120 Hz [36]. In order to suppress the voltage ripple onVo , a resonant controller [35] as (32) is added onto the voltageloop, generating an infinite loop gain at 120 Hz. This resonant(at 60 Hz) controller can be applied to ac current loop as well

Rov(s) = ks

s2 + (2ωo)2 . (32)

In addition, the loop-gain at 120 Hz provided by the dc-link voltage controller Hv is not very small. Hence, relativelylarge 120-Hz components are still included in the output ofthe dc-link voltage controller vc , which is also the ac currentmagnitude reference. The ac current has a considerable third-order harmonic component due in large to this effect [36].

The notch filter N in (33) [37] can be used here to block the120-Hz component in the voltage loop. The current loop canbenefit from implementing this filter by reducing the 120-Hzcomponent from vc

N(s) =(s/2ωo)2 + 1

(s/2ωo)2 + s 12ωo Qo

+ 1. (33)

The dc-link voltage decoupling terms are applied in bothcontrollers’ current loops as depicted in Fig. 12, to reduce theloop-gain variation due to the low-frequency dynamics of dc-link voltage (120 Hz) in (26) and (30).

The variation of the ac grid should be also considered, espe-cially during weak grid conditions when the high-frequency dy-namics of the grid cannot be ignored. Based on (27) and shownin Fig. 13, an additional small-signal perturbation from the grid,vac , is added into the current loop. vab is the H-bridge termi-nal voltage. The perturbation can be thereby canceled, though

Fig. 13. Simplified ac current loop with disturbance rejection.

not totally, by the disturbance rejection term (vac /vdc) in thecontroller, as shown in Fig. 13.

All the aforementioned small-signal transfer functions areused to design the multipole/zero linear controllers with thedesired control bandwidth and phase/gain margins.

V. VOLUME COMPARISON AND HARDWARE DEVELOPMENT

An extra dc LC filter (Lo , Co ) is required for the second-stage converter to produce a constant dc-bus voltage. The smalldc-link capacitor will have an impact on the size of the dc-sidefilter, and the total volume should be evaluated by consideringall the parameters.

The design of dc inductor Lo and capacitor Co are basedon the average current ripple Δio and capacitor voltage rippleΔvo , as shown below in (34) and (35). The physical design ofLo should consider the maximum value of Io when vdc reachesthe maximum value to avoid the core saturation

Lo = Ts(1 − D) Vo

2Δio=

Ts

2Δio

(Vo −

V 2o

Vav

)(34)

Co = TsΔio8Δvo

. (35)

The first-stage ac-side inductor Lac is designed based on theripple current requirement (e.g., <25%Iac rms). The second-stage ac-side inductor Lac2 is designed to meet the currentharmonics requirement specified in [18]. The design of theac DM capacitor CDM is limited by the reactive power level(e.g., <2.5%Prate). The detailed design equations can be foundin [38].

The system theoretical design parameters and volume of thepassive and active components by using unipolar modulation[38] at 20-kHz switching frequency are shown in Table II. Thedc-link capacitor volume is calculated based on the availabilityof the film-type capacitor (450-V rating for Co , 800-V ratingfor Cdc) from the market. The inductor volume is calculated bychoosing the amorphous alloy magnetic core due to the highsaturation flux-density and low high-frequency core loss.

The results show that, for the dc nanogrid application, a largepower-density improvement is accomplished by the two-stage


Fig. 14. 10-kW ECC converter prototype.

Fig. 15. System test setup.

Fig. 16. 10-kW rectification mode test. Vac [200 V/DIV], Iac [50 A/DIV],Vdc [200 V/DIV], and Vo [200 V/DIV].

topology with dc-link capacitor reduction besides the fulfillmentof requirements of ECC.

A 10-kW high-power-density bidirectional PWM converter isdeveloped as shown in Fig. 14. A fifth generation 1200 V/150 Athree-phase IGBT module and a pin-type heatsink with fans areused as the active component and cooling device in the system.

Fig. 17. 5.9-kW regeneration mode test. Vac [200 V/DIV], Iac [50 A/DIV],Vdc [200 V/DIV], and Vo [200 V/DIV].

Fig. 18. 6-kW rectification mode test. Vac [200 V/DIV], Iac [50 A/DIV], Vdc[200 V/DIV], and Vo [5 V/DIV].

Besides the main components, the dc and ac-side EMI filter arealso implemented in the system.

VI. EXPERIMENTAL EVALUATION

The ac/dc system test setup is shown in Fig. 15, whichincludes one 25 kVA split-phase single-phase transformer tosupply 240-V rms ac bus, the ECC converter, the BDC, andone ac power supply. It should be noted that the BDC isa discontinuous-current-mode (DCM) three-phase interleaveddc–dc converter [11], and the battery is a 330-V lithium-ionbatteries pack manufactured by Saft. An ac power supply emu-lates the grid, and the BDC injects the power into the dc system.There are loads on both the ac and dc sides. If the injected dcpower is less than that required by the dc load, the converter willregenerate the power from the dc-side to ac-side.


Fig. 19. Mode transition between rectification mode and regeneration mode.Vac [200 V/DIV], Iac [10 A/DIV], Vdc [20 V/DIV], and Vo [20 V/DIV].

Fig. 20. 6-kW rectification mode test without notch filter. Vac [200 V/DIV],Iac [50 A/DIV], Vdc [200 V/DIV], and Vo [200 V/DIV].

Fig. 21. 6-kW rectification mode test with notch filter. Vac [200 V/DIV], Iac[50 A/DIV], Vdc [200 V/DIV], and Vo [200 V/DIV].

Fig. 22. 6-kW rectifier mode test without grid perturbation cancellation term.Vac [200 V/DIV], Iac [50 A/DIV], Vdc [200 V/DIV], and Vo [200 V/DIV].

Fig. 23. 6-kW rectifier mode test with grid perturbation cancellation term.Vac [200 V/DIV], Iac [50 A/DIV], Vdc [200 V/DIV], and Vo [200 V/DIV].

Fig. 24. 3-kW transient step test. Vac [500 V/DIV], Iac [50 A/DIV], Vdc[100 V/DIV], and Vo [20 V/DIV].


Bidirectional power tests under rectification mode (ac to dc)and regeneration mode (dc to ac) are shown in Figs. 16 and 17,respectively. For the regeneration mode test, total 5.9-kW poweris generated by dc source. 1.5-kW loads are placed on the dc-side, while the 4.4-kW power is dispatched to the grid. Fig. 18shows the results under a 6-kW condition that the advancedcontrol regulates the dc nanogrid bus Vo at 380 V with a smallvoltage ripple (<2 Vpp ); even the ripple of dc-link voltage Vdcis relatively large (120 Vpp ) due to the reduction of the dc-linkcapacitor Cdc . The seamless transition from the rectificationmode to the regeneration mode is shown in Fig. 19. This showsthat the energy flows freely in either direction between the acand dc sides without affecting the dc-bus voltage Vo .

Figs. 20 and 21 show how the notch filter improves the accurrent regulation performance as discussed earlier. It is seenthat, in comparison with Fig. 21, the ac current in Fig. 20 bearsrelatively large third-order current harmonics without the notchfilter. The ac current waveforms under regeneration mode areshown without and with the grid voltage perturbation cancel-lation terms in Figs. 22 and 23, respectively. The THD of thecurrent is also improved by adding this additional term to thecontroller. Finally, Fig. 24 shows the 3-kW load-step transientresponse result when the dc current source pumps the dc current.The converter jumps from rectification mode to regenerationmode, while a dc-link voltage spike of only 30 V is observeddue to the fast response of the dc-link voltage.

Several more system-level tests between the BDC and ECCunder different modes are also conducted, which is howeverbeyond the scope of this paper and will be presented in future.

VII. CONCLUSION

The ECC converter, the key component in the future more-electronic distribution system and its functions are proposed,which includes the dynamics decoupling, bidirectional powerflow operation, bidirectional fault-current interruption, powermetering, and communications.

A dc electronic distribution system (dc nanogrid) in residen-tial buildings as one of the future distribution system solutionsto integrate multi-RES, energy storage devices, and electronicloads is presented. A single-phase two-stage bidirectional con-verter for the dc nanogrid application is proposed to effectivelyreduce the impact of ripple energy on dc system operation. Asignificant dc-link capacitor reduction is achieved but the dy-namics decoupling and bidirectional current protection are stillprovided.

With the goal of realizing this converter, a bidirectional con-trol structure and design procedure are presented and verifiedby experiments. Besides the dc nanogrid, this converter is alsoapplicable as a high power-density BDC for electric vehicle andother energy-storage applications.

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Dong Dong (S’09) received the B.S. degree from Ts-inghua University, Beijing, China, in 2007, and theM.S. degree in electrical engineering from VirginiaPolytechnic Institute and State University, Blacks-burg, in 2009, where he is currently working towardthe Ph.D. degree in Center for Power ElectronicsSystems.

His research interests include modeling and con-trol of single-phase to multiphase power converters,high-power converter design for utility application,passive components and electromagnetic interference

filter design, and the system integration design for renewable energy systemsand dc power distribution systems.

Igor Cvetkovic (S’10) received the Dipl. Ing. de-gree in power systems from the University of Bel-grade, Belgrade, Serbia, in 2004, and the M.S. de-gree in 2010 from Center for Power Electronics Sys-tems,Virginia Polytechnic Institute and State Univer-sity (Virginia Tech), Blacksburg, where he is cur-rently working toward the Ph.D. degree.

For few years, he was with the Electric PowerIndustry of Serbia before joining Virginia Tech. Hisresearch interests include dc-electronic power distri-bution systems stability and design, as well as power

electronics systems modeling and control.

Dushan Boroyevich (S’81–M’86–SM’03–F’06) re-ceived the Dipl. Ing. degree from the University ofBelgrade Belgrade, Serbia, in 1976, and the M.S.degree from the University of Novi Sad, Novi Sad,Serbia, in 1982, and the Ph.D. degree in 1986 fromVirginia Polytechnic Institute and State University(Virginia Tech), Blacksburg.

From 1986 to 1990, he was an Assistant Professorand the Director of the Power and Industrial Elec-tronics Research Program in the Institute for Powerand Electronic Engineering, at the University of Novi

Sad, and later, acting as the Head of the Institute. He then joined the BradleyDepartment of Electrical and Computer Engineering, Virginia Tech as an As-sociate Professor, where he is currently the American Electric Power Professorat the department and the Co-Director of the Center for Power Electronics Sys-tems. His research interests include multiphase power conversion, electronicpower distribution systems, power electronics systems modeling and control,and multi-disciplinary design optimization.

Dr. Boroyevich is a recipient of the IEEE William E. Newell Power Elec-tronics Technical Field Award. He is the 2011–2012 President of IEEE PowerElectronics Society.

Wei Zhang (S’09) received the B.S. degree in elec-trical engineering from Xi’an Jiaotong University,Xi’an, China, in 2006, and the M.S. degree inpower electronics from Zhejiang University, Zhe-jiang, China, in 2009. He is currently working towardthe Ph.D. degree at the Center for Power Electron-ics Systems, Virginia Polytechnic Institute and StateUniversity, Blacksburg.

His main research interests include high volt-age and high power lithium-ion battery management,high efficiency and high power density dc–dc conver-

sion, and soft switching techniques.

Ruxi Wang (S’10) received the B.S. and M.S. de-grees in electrical engineering from Xi’an Jiao-tong University, Xi’an, China, and the Ph.D. degreein the Center for Power Electronics Systems, Vir-ginia Tech, Blacksburg, in 2004, 2007, and 2012,respectively.

In 2012, he joined the Global Research Centerof General Electric Company, Niskayuna, USA asan electrical engineer. His research interests includehigh-power-density, high-temperature converter de-sign, passive filter design and electromagnetic inter-

ference technology, advanced components and packaging technology.

Paolo Mattavelli (S’95–A’96–M’00–SM’10) re-ceived the Master’s (Hons.) and the Ph.D. degree inelectrical engineering from the University of Padova,Padova, Italy, in 1992 and 1995, respectively.

From 1995 to 2001, he was a Researcher at theUniversity of Padova. From 2001 to 2005, he was anAssociate Professor the University of Udine, wherehe led the Power Electronics Laboratory. In 2005, hejoined the University of Padova in Vicenza with thesame duties and since 2010, he has been with Vir-ginia Polytechnic Institute and State University as a

Professor and a member of the Center for Power Electronics Systems. His mainresearch interests include analysis, modeling, and analog and digital controlof power converters, grid-connected converters for renewable energy systemsand microgrids, high-temperature, and high-power density power electronics.In these research fields, he has been leading several industrial and governmentprojects.

Dr. Mattavelli has been serving as an Associate Editor for IEEE TRANSAC-TIONS ON POWER ELECTRONICS since 2003. From 2005 to 2010, he was theIndustrial Power Converter Committee Technical Review Chair for the IEEETRANSACTIONS ON INDUSTRY APPLICATIONS. During 2003–2006 and 2006–2009, he was also a Member-at-Large of the IEEE Power Electronics Society’sAdministrative Committee. He also received in 2005 and 2006 the Prize PaperAward in the IEEE TRANSACTIONS ON POWER ELECTRONICS and in 2007, asecond place in the Prize Paper Award at the IEEE Industry Application AnnualMeeting.

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