© 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda...

© 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian Serda

Semiconductor Manufacturing Technology

Michael Quirk & Julian Serda © October 2001 by Prentice Hall

Chapter 9

IC Fabrication Process Overview

Semiconductor Manufacturing Technology

Michael Quirk & Julian Serda © October 2001 by Prentice Hall

Chapter 9

IC Fabrication Process Overview


Major Fabrication Steps in MOS Process Flow

Used with permission from Advanced Micro Devices

Figure 9.1


Oxidation(Field oxide)

Silicon substrate

Silicon dioxideSilicon dioxide

oxygen

PhotoresistDevelop

oxideoxide

PhotoresistCoating

photoresistphotoresist

Mask-WaferAlignment and Exposure

Mask

UV light

Exposed Photoresist

exposedphotoresistexposed

photoresist

GGS D

Active Regions

top nitridetop nitride

S DGG

silicon nitridesilicon nitride

NitrideDeposition

Contact holes

S DGG

ContactEtch

Ion Implantation

resis

t

resis

t

resis

t

resis

t

oxox D

G

Scanning ion beam

S

Metal Deposition and

Etch

drainS DGG

Metal contacts

PolysiliconDeposition

polysiliconpolysilicon

Silane gas

Dopant gas

Oxidation(Gate oxide)

gate oxidegate oxide

oxygen

PhotoresistStrip

oxideoxide

RF P

ower

RF P

ower

Ionized oxygen gas

OxideEtch

photoresistphotoresistoxideoxide

RF P

ower

RF P

ower

Ionized CF4 gas

PolysiliconMask and Etch

RF P

ower

RF P

ower

oxideoxideoxideoxide

Ionized CCl4 gas

poly

gat

e

poly

gat

e

RF P

ower

RF P

ower


CMOS Process Flow

• Overview of Areas in a Wafer Fab– Diffusion– Photolithography– Etch– Ion Implant– Thin Films– Polish

• CMOS Manufacturing Steps

• Parametric Testing


Model of Typical Wafer Flow in a Sub-Micron CMOS IC Fab

Test/Sort Implant

Diffusion Etch

Polish

PhotoCompleted Wafer

Unpatterned Wafer

Wafer Start

Thin Films

Wafer Fabrication (front-end)


Figure 9.2


1. Twin-well Implants

2. Shallow Trench Isolation

3. Gate Structure

4. Lightly Doped Drain Implants

5. Sidewall Spacer

6. Source/Drain Implants

7. Contact Formation

8. Local Interconnect

9. Interlayer Dielectric to Via-1

10. First Metal Layer

11. Second ILD to Via-2

12. Second Metal Layer to Via-3

13. Metal-3 to Pad Etch

14. Parametric Testing

Passivation layer Bonding pad metal

p+ Silicon substrate

LI oxide

STI

n-well p-well

ILD-1

ILD-2

ILD-3

ILD-4

ILD-5

M-1

M-2

M-3

M-4

Poly gate

p- Epitaxial layer

p+p+

ILD-6

LI metal

Via

p+p+ p+p+ n+n+n+ 2

3

1

4

5

67

8

9

10

11

12

13

14

CMOS Manufacturing Steps


n-well Formation

3

1

2

Photo

Im plant

D iffusion

4

Polish

E tch

5

Thin F ilm s

~5 um

(D ia = 200 m m , ~2 m m thick)

Photoresist

Phosphorus im plant

3

1

2

p+ S ilicon substrate

p- Epitaxia l layer

O xide

5

n-well4

Figure 9.8


p-well Formation

Thin F ilm s

3

1

2

Photo

Im plant

D iffusion

P olish

E tch


Boron im plant

Photoresist1

p- Epitaxia l layer

O xide

3n-well 2 p-well

Figure 9.9


STI Trench Etch

Thin F ilm s

1 2

Photo

Polish

E tch

Im plant

D iffusion

3 4

+Ions

Selective etch ing opens iso lation regions in the epi layer.


p- Epitaxia l layer

n-w ell p-w ell

3 Photoresist

2 Nitride 4

1 O xide

STI trench

Figure 9.10


STI Oxide Fill

1

2

D iffusion

Polish

E tchPhoto

Im plant

Thin F ilm s

p-w ell

Trench fill by chem ica l vapor deposition

1

Liner oxide


p- Epitaxia l layer

n-w ell

2

N itride

Trench C VD oxide

O xide

Figure 9.11


STI Formation

Thin F ilm s

1

2

D iffusion E tchPhoto

Im plant

Polish

p-w ell

1

2

Planarization by chem ica l-m echanica l po lish ing

STI oxide after po lish

L iner oxide


p- Epitaxia l layer

n-w ell

N itride strip

Figure 9.12


Poly Gate Structure Process

Thin F ilm s

1 2


Im plant

Polish

3 4


G ate oxide1

2

p- Epitaxia l layer

n-well p-well

Polysilicon deposition Poly gate etch4

3 Photoresist

ARC

Figure 9.13


n LDD Implant

Thin F ilm s

1

2


Im plant

Polish


p- Epitaxia l layer

n-w ell p-w elln-n-n-

1 Photoresist m ask

Arsenic n- LD D im plant2

Figure 9.14


p LDD Implant

1

2


Im plant

PolishThin F ilm s


p- Epitaxia l layer

n-w ell p-w ell

Photoresist M ask1

p-p-

Photoresist m ask1

n-n-

2 BF p- LD D im plant2

p-n-

Figure 9.15


Side Wall Spacer Formation

1

2


Im plant

PolishThin F ilm s +Ions


p- Epitaxia l layer

n-w ell p-w ellp-p-

1 Spacer oxide S ide wall spacer

2 Spacer etchback by anisotropic p lasm a etcher

p-n- n-n-

Figure 9.16


n+ Source/Drain Implant

Thin F ilm s

1

2


Im plant

Polish

p+ S ilicon substra te

p- Epitaxia l layer

n-w ell p-w elln+

Arsenic n+ S /D im plant2

Photoresist m ask1

n+ n+

Figure 9.17


p+ Source/Drain Implant

1

2


PolishThin F ilm s

Im plant

3

Boron p+ S /D im plant2


p- Epitaxia l layer

n-w ell p-w ell

Photoresist M ask11 Photoresist m ask

n+ p+ p+ n+ n+ p+

Figure 9.18


Contact Formation

Thin F ilm s

1 2


Im plant

Polish3 2 Tisilic ide contact form ation (anneal)Titanium etch3

Titanium depostion1

n+ p+ n-well p+ n+ p-well n+ p+

p- Epitaxia l layer


Figure 9.19


LI Oxide as a Dielectric for Inlaid LI Metal (Damascene)

L I m e ta l

L I o x id e

Figure 9.20


LI Oxide Dielectric Formation

1 N itride C VD

p-w ellp-w ell

p- Epitaxia l layer


LI oxide

2 D oped oxide CVD

4 LI oxide etchO xide polish3


Im plant

Polish

3

4

2

1Thin F ilm s

Figure 9.21


LI Metal Formation

Thin F ilm s

D iffusion Photo

Im plant

321 4

Etch

Polish

n-well

LI tungsten polishTungsten deposition

Ti/T iN deposition2

3 4

LI oxide

Ti deposition1 p-well

p- Epitaxia l layer


Figure 9.22


Via-1 Formation


Im plant

Polish

3

2

1Thin F ilm s

O xide polishILD -1 oxide etch(Via-1 form ation)2 3

LI oxide

ILD -1 oxide deposition

1

ILD-1

p-w elln-w ell

p- Epitaxia l layer


Figure 9.23


Plug-1 Formation

Thin F ilm s

D iffusion Photo

Im plant

321 4

Etch

Polish

Tungsten polish (P lug-1)TungstendepositionTi/T iN

deposition23

4

LI oxide

Ti dep.1 ILD-1

p-welln-well

p- Epitaxia l layer


Figure 9.24


SEM Micrographs of Polysilicon, Tungsten LI and Tungsten Plugs

Micrograph courtesy of Integrated Circuit Engineering

PolysiliconTungsten LI

Tungsten plug

Mag. 17,000 X

Photo 9.4


Metal-1 Interconnect Formation

2 3 41

TiN deposition

A l + C u (1% )deposition

Ti D eposition

LI oxide

ILD-1

M etal-1 etch

p-welln-well

p- Epitaxia l layer


Photo E tchD iffus ion

Im plant

4

1 32

PolishThin F ilm s

Figure 9.25


SEM Micrographs of First Metal Layer over First Set of Tungsten Vias

Micrograph courtesy of Integrated Circuit Engineering

TiN metal cap

Mag. 17,000 XTungsten plug

Metal 1, Al

Photo 9.5


4


p- Epitaxia l layer

n-w ell p-w ell

LI oxide

ILD-1

O xide polish

ILD-2 gap fill1

32

ILD -2 oxide deposition

ILD -2 oxide etch(Via-2 form ation)

Photo E tch

Polish

D iffusion

Im plant

4

2 31

Thin F ilm s

Via-2 Formation

Figure 9.26


Plug-2 Formation

LI oxide

Tungsten deposition (P lug-2)

Ti/T iN deposition2

3

Ti deposition1

ILD-1

ILD-2


p- Epitaxia l layer

n-well p-well

Tungstenpolish4

Thin F ilm s

D iffusion Photo

Im plant

321 4

Etch

Polish

Figure 9.27


Metal-2 Interconnect Formation


p- Epitaxia l layer

n-well p-well

G ap fill

3 Via-3/P lug-3 form ationM eta l-2 depositionto etch

ILD -3 oxidepolish

2

14

LI oxide

ILD -1

ILD -2

ILD -3

Figure 9.28


Full 0.18 m CMOS Cross Section

Figure 9.29

Passivation layer Bonding pad metal

p+ Silicon substrate

LI oxide

STI

n-well p-well

ILD-1

ILD-2

ILD-3

ILD-4

ILD-5

M-1

M-2

M-3

M-4

Poly gate

p- Epitaxial layer

p+p+n+

ILD-6

LI metal

Via

p+p+ p+p+ n+n+


SEM Micrograph of Cross-section of AMD Microprocessor

Micrograph courtesy of Integrated Circuit EngineeringMag. 18,250 X

Photo 9.6


Wafer Electrical Test using a Micromanipulator Prober(Parametric Testing)

Photo courtesy of Advanced Micro Devices

Photo 9.7

© 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda...

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Transcript of © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda...