VHDL Hardware VHDL Hardware Description LanguageDescription Language

GUIDELINESGUIDELINES How to write HDL code:How to write HDL code:

Q

QSET

CLR

D

Q

QSET

CLR

D

GUIDELINESGUIDELINES How NOT to write HDL code:How NOT to write HDL code:

if a=b thenx=a^b

else if a>b then...

Think Hardware NOT Think Hardware NOT SoftwareSoftware

Poorly written VHDL code will Poorly written VHDL code will either be:either be:– UnsynthesizableUnsynthesizable– Functionally incorrectFunctionally incorrect– Lead to poor performance/area/power Lead to poor performance/area/power

resultsresults

VHDL code basic structureVHDL code basic structure

EntityEntity(I/O and generic declaration(I/O and generic declaration))

ArchitectureArchitecturestructural (structure descriptionstructural (structure description))rtl (register transfer level descriptionrtl (register transfer level description))behavioral (high-level descriptionbehavioral (high-level description))

Entity declarationEntity declaration

ENTITY ENTITY entity_nameentity_name ISISPORT (PORT (port_name_1 port_name_1 : : port_type_1;port_type_1;

port_name_2port_name_2: : portport _ _type_2;type_2; . . . . . . port_name_nport_name_n: port_type_n);: port_type_n); END END entity_nameentity_name;;

Port typesPort types PORT DIRECTIONPORT DIRECTION

- IN- IN-OUT-OUT-INOUT-INOUT

SIGNAL TYPESIGNAL TYPE– BITBIT– BIT_VECTOR(BIT_VECTOR(WIDTH -1 WIDTH -1 DOWNTO 0)DOWNTO 0)– STD_LOGICSTD_LOGIC– STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(WIDTH -1 WIDTH -1 DOWNTO 0)DOWNTO 0)

Entity declaration example Entity declaration example (1/2)(1/2)

ENTITY ENTITY and_gate and_gate ISISPORT (PORT (i1: IN BIT;i1: IN BIT;

i2: IN BIT;i2: IN BIT; O: OUT BITO: OUT BIT););END END and_gate;and_gate;

Entity declaration example Entity declaration example (2/2)(2/2)

Library ieee;Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_1164.all;

ENTITY ENTITY adder adder ISISPORT (PORT (i1: IN STD_LOGIC_VECTOR(3 DOWNTO 0);i1: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

i2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);i2: IN STD_LOGIC_VECTOR(3 DOWNTO 0); sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); carry: OUT STD_LOGICcarry: OUT STD_LOGIC););END END adder;adder;

ExampleExample

COUNTER

EN

PRESET

5

COUNT

5

CLK RST

Architecture Architecture declarationdeclaration

ARCHITECTURE ARCHITECTURE architecture_name architecture_name OF OF entity_name entity_name ISIS

component declaration;component declaration; signal declaration;signal declaration; BEGINBEGIN component instantiationcomponent instantiation sequential statementssequential statements ( (processes)processes) concurrent statementsconcurrent statements END END [architecture_name];[architecture_name];

Component Component declarationdeclaration

COMPONENT COMPONENT component_namecomponent_name PORT (PORT (port_name_1 port_name_1 : : port_type_1;port_type_1; port_name_2port_name_2: : portport _ _type_2;type_2; . . . . . . port_name_nport_name_n: port_type_n);: port_type_n); END COMPONENT;END COMPONENT;

Component declaration Component declaration exampleexample

COMPONENT COMPONENT and_gateand_gatePORT (PORT (i1: IN BIT;i1: IN BIT;

i2: IN BIT;i2: IN BIT; O: OUT BITO: OUT BIT););END COMPONENTEND COMPONENT;;

Signal declarationSignal declarationSIGNAL SIGNAL signal_name : signal_name : signal_typesignal_type;;

ExamplesExamples

SIGNAL SIGNAL data_bus: std_logic_vector(7 downto data_bus: std_logic_vector(7 downto 0);0);

SIGNAL SIGNAL clock: std_logic;clock: std_logic;SIGNAL SIGNAL count : bit_vector(5 downto 0);count : bit_vector(5 downto 0);

Component instantiation Component instantiation (nominal(nominal))

Label: component_nameLabel: component_name PORT MAP( PORT MAP( port_name1 => port_name1 =>

signal_name1,signal_name1, port_name2 => port_name2 =>

signal_name2,signal_name2, … … port_nameN => port_nameN =>

signal_nameN);signal_nameN);

ExampleExample

U_adder:U_adder: adderadderPORT MAP(PORT MAP(i1 => add1,i1 => add1,

i2 => add2,i2 => add2, sum => s,sum => s, carry => c);carry => c);

Component instantiation Component instantiation (positional(positional))

Label: component_nameLabel: component_name PORT MAP( PORT MAP( signal_name1,signal_name1, signal_name2,signal_name2, … … signal_nameN);signal_nameN);

ExampleExample

U_adder:U_adder: adderadderPORT MAP(PORT MAP(add1,add1,

add2,add2, s,s, c);c);

Structural description example Structural description example (1/2)(1/2)

i0i1

i2i3

o

S1

S2

ENTITY gates IS

PORT (i0,i1,i2,i3: std_logic;

o: out std_logic);

END gates;

ARCHITECTURE str of gates IS

COMPONENT and_gatePORT (i1,i2: in std_logic; o: out std_logic);END COMPONENT;SIGNAL s1,s2: std_logic;BEGIN

Structural description example Structural description example (2/2)(2/2)

i0i1

i2i3

o

S1

S2

U_and1: and_gatePORT MAP(i1 => i0, i2 => i1,

o => s1);U_and2: and_gatePORT MAP(i1 => i2, i2 => i3,

o => s2);U_and3: and_gatePORT MAP(i1 => s1, i2 => s2,

o => o);END;

VHDL operatorsVHDL operators

• ArithmeticArithmetic++, - , *, , - , *, SynthesizableSynthesizable

/, abs, rem, mod, **/, abs, rem, mod, ** Non-synthesizableNon-synthesizable• LogicalLogicalAND, OR, NOT, NAND, NOR, XOR, XNORAND, OR, NOT, NAND, NOR, XOR, XNOR• RelationalRelational=, /=, <, >, <=, >==, /=, <, >, <=, >=

Signal assignmentSignal assignmentsignal_name <= signal_name <= signal_value;signal_value;

ExamplesExamplessignal a: std_logic;signal a: std_logic;signal b: std_logic_vector(6 downto 0);signal b: std_logic_vector(6 downto 0);signal c: std_logic_vector(3 downto 0);signal c: std_logic_vector(3 downto 0);signal d: std_logic_vector(2 downto 0);signal d: std_logic_vector(2 downto 0);

CorrectCorrect IncorrectIncorrecta <= ‘1’;a <= ‘1’; a <= “01”;a <= “01”;b <= “0101001”;b <= “0101001”; b <= ‘0’;b <= ‘0’;b(1) <= ‘0’;b(1) <= ‘0’;c <= (others => ‘0’);c <= (others => ‘0’); c <= ‘0000’;c <= ‘0000’;d <= (1 => ‘0’, others => ’1’);d <= (1 => ‘0’, others => ’1’); d <= b & c;d <= b & c;b <= c & d;b <= c & d; b(3 downto 1) <= d(1 downto 0);b(3 downto 1) <= d(1 downto 0);b(5 downto 3) <= d;b(5 downto 3) <= d;

The “after” clauseThe “after” clauseUsed to assign signals with delay, modeling circuit Used to assign signals with delay, modeling circuit

behaviourbehaviour a <= d after 5 ns;a <= d after 5 ns; -- 5 ns wire delay-- 5 ns wire delay b <= a and c after 20 ns;b <= a and c after 20 ns; -- 20 ns gate delay-- 20 ns gate delayNot synthesizableNot synthesizable, is ignored by synthesis tools, is ignored by synthesis toolsUseful in testbenches for creating input signal Useful in testbenches for creating input signal

waveformswaveforms clk <= not clk after 20 ns; -- 40 ns clock periodclk <= not clk after 20 ns; -- 40 ns clock period rst_n <= ‘0’,rst_n <= ‘0’,

‘‘1’ after 210 ns;1’ after 210 ns;

Concurrent statements Concurrent statements –delta time–delta time

b <= not a;b <= not a; (a = ‘1’, b = ‘1’, c= (a = ‘1’, b = ‘1’, c= ‘0’)‘0’)

c <= a xor b;c <= a xor b;

TimeTime aa bb cc 00 11 11 00

b <= not a;b <= not a; (a = ‘1’, b = ‘1’, c= ‘0’)(a = ‘1’, b = ‘1’, c= ‘0’)c <= a xor b;c <= a xor b;

TimeTime aa bb cc 00 11 11 00 δδ 11 00 002δ2δ 11 0 0 11

b <= not a;b <= not a; (a = ‘1’, b = ‘1’, c =‘0’)(a = ‘1’, b = ‘1’, c =‘0’)c <= a xor b;c <= a xor b;

TimeTime aa bb cc 00 11 11 00 δδ 11 00 00

Concurrent statementsConcurrent statements Multiple driver errorMultiple driver error

c <= a AND b;c <= a AND b;……..c <= d OR e;c <= d OR e;

ab

de

c

Combinational circuit Combinational circuit descriptiondescription

ENTITY gates isENTITY gates is port (a: in std_logic;port (a: in std_logic; d: out std_logic);d: out std_logic);end gates;end gates;

Architecture rtl of gates isArchitecture rtl of gates issignal b: std_logic;signal b: std_logic;beginbegin b <= not a;b <= not a; d <= c xor b; --d<=c xor (not a);d <= c xor b; --d<=c xor (not a);end rtl;end rtl;

ab

cd

GENERATE GENERATE STATEMENTS STATEMENTS

(concurrent only)(concurrent only) Used to generate multiple instances Used to generate multiple instances

of a component in homogeneous of a component in homogeneous architecturesarchitectures

Z_Gen: For i in 0 to 7 generateZ_Gen: For i in 0 to 7 generatez(i) <= x(i) AND y(i+8);z(i) <= x(i) AND y(i+8);

end generate;end generate;

Generate example Generate example (1/2)(1/2)

Cell Cell Cell Cell

i0 i1 i2 i3

o0 o1 o2 o3

‘0’ ‘0’

Cell

o_ south

o_ east

i_ east

i_ west

o_ west

i_ north

. . . Cell

i 63

o63

ENTITY cell_array IS PORT (i: in std_logic_vector(63 downto 0); o: out std_logic_vector(63 downto 0) );END ENTITY cell_array;

ARCHITECTURE str OF cell_array ISCOMPONENT cell PORT (i_north: in std_logic; i_west: in std_logic; i_east: in std_logic; o_east: out std_logic; o_west: out std_logic; o_south: out std_logic );end component; signal west: std_logic_vector(62 downto 0); signal east: std_logic_vector(62 downto 0);BEGIN

Generate Generate example example

(2/2)(2/2)

U_cell_0: cell PORT MAP (i_north => i(0), i_west => '0', i_east => west(0), o_east => east(0), o_west => open, o_south => o(0) ); U_cell_63: cell PORT MAP (i_north => i(63), i_west => east(62), i_east => '0', o_east => open, o_west => west(62), o_south => o(63) ); U_top_gen: for i in 1 to 62 generate U_cell_i: cell PORT MAP (i_north => i(i), i_west => east(i-1), i_east => west(i), o_east => east(i), o_west => west(i-1), o_south => o(i) ); end generate; end;

Cell Cell Cell Cell

i0 i1 i2 i3

o0 o1 o2 o3

‘0’ ‘0’

Cell

o_ south

o_ east

i_ east

i_ west

o_ west

i_ north

. . . Cell

i 63

o63

Generate example 2 (1/5)Generate example 2 (1/5)

Cell Cell Cell Cell

Cell Cell Cell Cell

Cell Cell Cell Cell

Cell Cell Cell Cell

i0 i1 i2 i3

o0 o1 o2 o3

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

Cell

o_ south

o_east

i_east

i_west

o_west

i_north

ENTITY cell_array IS PORT (i: in std_logic_vector(3 downto 0); o: out std_logic_vector(3 downto 0) );END ENTITY cell_array;

--ARCHITECTURE str OF cell_array ISCOMPONENT cell PORT (i_north: in std_logic; i_west: in std_logic; i_east: in std_logic; o_east: out std_logic; o_west: out std_logic; o_south: out std_logic );end component; type sig_array is array (3 downto 0) of std_logic_vector(3 downto 0); type sig_array2 is array (2 downto 0) of std_logic_vector(3 downto 0); signal south: sig_array2; signal west: sig_array; signal east: sig_array;

Generate example 2Generate example 2(2/5)(2/5)

BEGINU_cell_0_0: cell PORT MAP (i_north => i(0), i_west => '0', i_east => west(0)(0), o_east => east(0)(0), o_west => open, o_south => south(0)(0) );

U_cell_0_3: cell PORT MAP (i_north => i(3), i_west => west(0)(3), i_east => '0', o_east => east(0)(3), o_west => west(0)(3), o_south => south(0)(3) );

U_cell_3_0: cell PORT MAP (i_north => north(2)(0), i_west => '0', i_east => west(3)(0), o_east => east(3)(0), o_west => open, o_south => o(0) );

Cell Cell Cell Cell

Cell Cell Cell Cell

Cell Cell Cell Cell

Cell Cell Cell Cell

i0 i1 i2 i3

o0 o1 o2 o3

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

Cell

o_ south

o_east

i_east

i_west

o_west

i_north

Generate example Generate example 2 (3/5)2 (3/5)

U_cell_3_3: cell PORT MAP (i_north => north(2)(3), i_west => west(3)(3), i_east => '0', o_east => open, o_west => west(3)(3), o_south => o(3) ); U_top_gen: for i in 1 to 2 generate U_cell_i_0: cell PORT MAP (i_north => i(i), i_west => east(i-1)(0), i_east => west(i)(0), o_east => east(i)(0), o_west => west(i-1)(0), o_south => south(i)(0) ); end generate; U_bottom_gen: for i in 1 to 2 generate U_cell_i_3: cell PORT MAP (i_north => south(i)(2), i_west => east(i-1)(3), i_east => west(i)(3), o_east => east(i)(3), o_west => west(i-1)(3), o_south => o(i) ); end generate;

Cell Cell Cell Cell

Cell Cell Cell Cell

Cell Cell Cell Cell

Cell Cell Cell Cell

i0 i1 i2 i3

o0 o1 o2 o3

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

Cell

o_ south

o_east

i_east

i_west

o_west

i_north

Generate example 2 (4/5)Generate example 2 (4/5)U_left_gen: for i in 1 to 2 generate U_cell_0_i: cell PORT MAP (i_north => south(0)(i), i_west => '0', i_east => west(0)(i), o_east => east(0)(i), o_west => open, o_south => south(0)(i) ); end generate;

U_right_gen: for i in 1 to 2 generate U_cell_3_i: cell PORT MAP (i_north => south(2)(i), i_west => east(3)(i-1), i_east => '0', o_east => east(3)(i), o_west => west(3)(i-1), o_south => south(3)(i) ); end generate;

Cell Cell Cell Cell

Cell Cell Cell Cell

Cell Cell Cell Cell

Cell Cell Cell Cell

i0 i1 i2 i3

o0 o1 o2 o3

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

Cell

o_ south

o_east

i_east

i_west

o_west

i_north

Generate example 2 Generate example 2 (5/5)(5/5)

U_inner_gen_x: for i in 1 to 2 generate U_inner_gen_y: for j in 1 to 2 generate U_cell_i_j: cell PORT MAP (i_north => south(i-1)(j), i_west => east(i)(j-1), i_east => west(i)(j), o_east => east(i)(j), o_west => west(i)(j-1), o_south => south(i)(j) ); end generate; end generate;END ARCHITECTURE str;

Cell Cell Cell Cell

Cell Cell Cell Cell

Cell Cell Cell Cell

Cell Cell Cell Cell

i0 i1 i2 i3

o0 o1 o2 o3

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

Cell

o_ south

o_east

i_east

i_west

o_west

i_north

Arithmetic unit Arithmetic unit descriptiondescription

Library ieee;Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Use ieee.std_logic_unsigned.all;

ENTITY add1 isENTITY add1 is port (a, b: in std_logic;port (a, b: in std_logic; cin: in std_logic;cin: in std_logic; sum: out std_logic;sum: out std_logic; cout: out std_logic);cout: out std_logic); end add1;end add1;

ARCHITECTURE rtl of add1 isARCHITECTURE rtl of add1 isSignal s: std_logic_vector(1 downto 0);Signal s: std_logic_vector(1 downto 0);beginbegin s <= (‘0’ & a) + b + cin;s <= (‘0’ & a) + b + cin; sum <= s(0);sum <= s(0); cout <= s(1);cout <= s(1);end;end;

ExampleExample

Describe a 5-bit multiplier in Describe a 5-bit multiplier in VHDLVHDL..

When statement When statement (concurrent)– describing (concurrent)– describing

MUXsMUXsPort/signal <= value1 Port/signal <= value1 WHEN WHEN condition1condition1 [[ELSE ELSE value2 value2 when when condition2condition2 … …]] ELSE ELSE valueN;valueN;

ENTITY ENTITY mux ISmux IS PORT (PORT (i0: in std_logic;i0: in std_logic; i1: in std_logic;i1: in std_logic; s: in std_logic;s: in std_logic; o: out std_logic);o: out std_logic);END END mux;mux;

ARCHITECTURE rtl OF ARCHITECTURE rtl OF mux mux ISISBEGINBEGIN o <= i0 when s = ‘0’ else i1;o <= i0 when s = ‘0’ else i1;END RTL;END RTL;

with statement with statement (concurrent)– describing (concurrent)– describing

MUXsMUXsWITH WITH signal signal SELECTSELECT port/signal <= expression1 port/signal <= expression1 WHENWHEN value1, value1, expression2 expression2 WHEN WHEN value2,value2, … … expressionN expressionN WHEN OTHERS;WHEN OTHERS;

ENTITY ENTITY mux ISmux IS PORT (PORT (i0: in std_logic;i0: in std_logic; i1: in std_logic;i1: in std_logic; s: in std_logic;s: in std_logic; o: out std_logic);o: out std_logic);END END mux;mux;

ARCHITECTURE rtl OF ARCHITECTURE rtl OF mux mux ISISBEGINBEGINWITH WITH s s SELECTSELECT o <= i0 o <= i0 WHENWHEN ‘0’, ‘0’, i1 i1 WHEN OTHERSWHEN OTHERS;;END rtl;END rtl;

Sequential statementsSequential statements (1)(1)

processprocess[[process_name:process_name:] ] PROCESS (PROCESS (sensitivity listsensitivity list)) BEGINBEGIN sequential statementssequential statementsEND PROCESS END PROCESS [[process_nameprocess_name];];

COMBINATIONAL PROCESSCOMBINATIONAL PROCESS

PROCESSPROCESS(a, b, c)(a, b, c)BEGINBEGIN d <= (a d <= (a AND AND b) b) OR OR c;c;END PROCESS;END PROCESS;

ALL input signals must be in ALL input signals must be in sensitivity list or latches will sensitivity list or latches will be produced!be produced!

If statement If statement (sequential)– (sequential)–

describing MUXsdescribing MUXsIf If condition1 condition1 thenthen signal1signal1 <= value1; <= value1; signal2 <= signal2 <= value2;value2;elsif elsif condition2 condition2 thenthen signal1signal1 <= value3; <= value3; signal2 <= signal2 <= value4;value4; … … [[ELSE ELSE signal1signal1 <= valuen- <= valuen-

1;1; signal2 <= signal2 <= valuen;valuen;]]end if;end if;

ENTITY ENTITY mux ISmux IS PORT (PORT (i0: in std_logic;i0: in std_logic; i1: in std_logic;i1: in std_logic; s: in std_logic;s: in std_logic; o: out std_logic);o: out std_logic);END END mux;mux;

ARCHITECTURE rtl OF ARCHITECTURE rtl OF mux mux ISISBEGINBEGINprocess(i0, i1, s)process(i0, i1, s)BEGINBEGINIf s = ‘0’ thenIf s = ‘0’ then o <= i0;o <= i0;elseelse o <= i1;o <= i1;end if;end if;end process;end process;END END rtlrtl;;

CASE statement CASE statement (sequential)– describing (sequential)– describing

MUXsMUXsCASE CASE expression expression ISIS when when value1 =>value1 => signal1 <= signal1 <= value2;value2; signal2 <= signal2 <= value3;value3; when when value4 =>value4 => signal1 <= signal1 <= value4;value4; signal2 <= signal2 <= value5;value5; . . . . . . [when others =>[when others => signal1signal1 <= valuen-1; <= valuen-1; signal2 <= signal2 <= valuen;valuen;]]end CASE;end CASE;

ENTITY ENTITY mux ISmux IS PORT (PORT (i0: in std_logic;i0: in std_logic; i1: in std_logic;i1: in std_logic; s: in std_logic;s: in std_logic; o: out std_logico: out std_logic););END END mux;mux;

ARCHITECTURE rtl OF ARCHITECTURE rtl OF mux mux ISISBEGINBEGINprocess(i0, i1, s)process(i0, i1, s)BEGINBEGINCASE s ISCASE s ISWHEN ‘0’ =>WHEN ‘0’ => o <= i0;o <= i0;WHEN OTHERS =>WHEN OTHERS => s <= i1;s <= i1;end CASE;end CASE;end process;end process;END END rtlrtl;;

ExampleExample Describe a 3-bit 4-to-1 MUXDescribe a 3-bit 4-to-1 MUX

CLOCKED PROCESSCLOCKED PROCESS(Latch with asynchronous (Latch with asynchronous

reset)reset)PROCESS(clk, rst_n)PROCESS(clk, rst_n)BEGINBEGIN IF rst_n = ‘0’ THENIF rst_n = ‘0’ THEN q <= (others => ‘0’);q <= (others => ‘0’); ELSIF clk= ‘1’ THENELSIF clk= ‘1’ THEN q <= d;q <= d; END IF;END IF;END PROCESS;END PROCESS;

CLOCKED PROCESSCLOCKED PROCESS(Latch(Latch with synchronous with synchronous

reset)reset)PROCESSPROCESS(clk)(clk)BEGINBEGIN IF IF clk = ‘1’ clk = ‘1’ THENTHEN if if rst_n = ‘0’ thenrst_n = ‘0’ then q <= (others => ‘0’);q <= (others => ‘0’); else else q <= d;q <= d; end if;end if; END IF;END IF;END PROCESS;END PROCESS;

CLOCKED PROCESSCLOCKED PROCESS(Flip-flop with asynchronous (Flip-flop with asynchronous

reset)reset)PROCESSPROCESS(clk, rst_n)(clk, rst_n)BEGINBEGIN IF IF rst_n = ‘0’ rst_n = ‘0’ THENTHEN q <= (others => ‘0’);q <= (others => ‘0’); ELSIF ELSIF clk’event and clk= ‘1’ clk’event and clk= ‘1’ THENTHEN

q <= d;q <= d; END IF;END IF;END PROCESS;END PROCESS;

CLOCKED PROCESSCLOCKED PROCESS(Flip-flop with synchronous (Flip-flop with synchronous

reset)reset)PROCESSPROCESS(clk)(clk)BEGINBEGIN IF IF clk’event clk’event and and clk= ‘1’ clk= ‘1’ THENTHEN IF IF rst_n = ‘0’ rst_n = ‘0’ THENTHEN q <= (others => ‘0’);q <= (others => ‘0’); else else q <= d;q <= d; end if;end if; END IF;END IF;END PROCESS;END PROCESS;

for loop statement – shift for loop statement – shift registerregister

[[labellabel]: ]: for for identifier identifier in in rangerange looploop

statementsstatementsend loopend loop;;

ENTITY shift_reg is port(clk, rst_n: in std_logic; input: in std_logic; output: out std_logic);end shift_reg;

Architecture rtl of shift_reg is signal d: std_logic_vector(3 downto 0);begin process(clk, rst_n) begin if rst_n = ‘0’ then d <= (others => ‘0’); elsif rising_edge(clk) then d(0) <= input; for i in 0 to 3 loop d(i+1) <= d(i); end loop; end if; end process;output <= d(3);end;

CLOCKED VS CLOCKED VS COMBINATIONAL PROCESS COMBINATIONAL PROCESS

(1/2)(1/2)

MUX2X1

a

b

c

q

process(a, b, c)process(a, b, c)BEGINBEGINCASE c ISCASE c ISWHEN ‘0’ =>WHEN ‘0’ => q <= a;q <= a;WHEN OTHERS =>WHEN OTHERS => q <= b;q <= b;end CASE;end CASE;end process;end process;

process(clk, rst)process(clk, rst)BEGINBEGINIf rst = ‘1’ thenIf rst = ‘1’ then q <= ‘0’;q <= ‘0’;elsif elsif clkclk’’eventevent and and clk = ‘1’ clk = ‘1’ thenthenCASE c ISCASE c ISWHEN ‘0’ =>WHEN ‘0’ => q <= a;q <= a;WHEN OTHERS =>WHEN OTHERS => q <= b;q <= b;end CASE;end CASE;end if;end if;end process;end process;

MUX2X1

a

b

c

q

Q

QSET

CLR

D

clk

rst

CLOCKED VS CLOCKED VS COMBINATIONAL PROCESS COMBINATIONAL PROCESS

(2/2)(2/2)PROCESSPROCESS(a, b, c)(a, b, c)BEGINBEGIN d <= (a d <= (a AND AND b) b) OR OR c;c;END PROCESS;END PROCESS;a

b

c

d

PROCESSPROCESS(clk, rst)(clk, rst)BEGINBEGIN if if rst = ‘1’ rst = ‘1’ thenthen d <= ‘0’;d <= ‘0’;elsif elsif clk’event and clk= ‘1’ clk’event and clk= ‘1’ thenthen d <= (a d <= (a AND AND b) b) OR OR c;c;end if;end if;END PROCESS;END PROCESS;

ab

c

d

Q

QSET

CLR

D

clk

rst

EXAMPLE: BINARY EXAMPLE: BINARY UPCOUNTERUPCOUNTER

PROCESS(clk)PROCESS(clk)beginbegin if clk’event and clk=‘1’ thenif clk’event and clk=‘1’ then if rst_n = ‘0’ then –-synchronous resetif rst_n = ‘0’ then –-synchronous reset count <= (others => ‘0’);count <= (others => ‘0’); elseelse if en = ‘1’ then --count enableif en = ‘1’ then --count enable count <= count + ‘1’;count <= count + ‘1’; end if;end if; end if;end if; end if;end if;end process;end process;

EXAMPLEEXAMPLE DESCIBE A BINARY UP/DOWN DESCIBE A BINARY UP/DOWN

COUNTER WITH ENABLE THAT COUNTER WITH ENABLE THAT COUNTS UPTO 12 AND THEN COUNTS UPTO 12 AND THEN STARTS AGAIN FROM ZEROSTARTS AGAIN FROM ZERO

The integer typeThe integer type Signal Signal signal_name: signal_name: integer range integer range

range_low range_low to to range_highrange_high Examples:Examples:

– Signal count: integer range 0 to 63 -- 6-bit Signal count: integer range 0 to 63 -- 6-bit countercounter

– Signal k: integer range 0 to 3 -- 2-bit counterSignal k: integer range 0 to 3 -- 2-bit counter

Binary up counter ver2Binary up counter ver2ARCHITECTURE rtl of counter isARCHITECTURE rtl of counter issignal count: integer range 0 to 31; -- 5-bit countersignal count: integer range 0 to 31; -- 5-bit counterbeginbeginPROCESS(clk)PROCESS(clk) beginbegin if clk’event and clk=‘1’ thenif clk’event and clk=‘1’ then if rst_n = ‘0’ then –-synchronous resetif rst_n = ‘0’ then –-synchronous reset count <= 0;count <= 0; elseelse if en = ‘1’ then --count enableif en = ‘1’ then --count enable count <= count + 1;count <= count + 1; end if;end if; end if;end if; end if;end if; end process;end process;end;end;

TESTBENCHTESTBENCHEntity Entity testbench_name testbench_name isisend end testbench_name;testbench_name;

ARCHITECTURE ARCHITECTURE architecture_name architecture_name of of testbench_name testbench_name ISISCOMPONENT declarationCOMPONENT declarationSignal declaration --signal clk: std_logic:=‘0’;Signal declaration --signal clk: std_logic:=‘0’;BEGINBEGINComponent instantiationComponent instantiation

{ clk <= not clk after 40 ns; --80 ns clock period{ clk <= not clk after 40 ns; --80 ns clock period a <= ‘1’,a <= ‘1’, ‘ ‘0’ after 50 ns,0’ after 50 ns, ‘ ‘1’ after 100 ns; }1’ after 100 ns; }end;end;

TESTBENCH EXAMPLETESTBENCH EXAMPLE EntityEntity testbench testbench isis endend testbench; testbench;

ArchitectureArchitecture test test ofof testbench testbench isis

componentcomponent mux mux PORT (PORT (i0: in std_logic;i0: in std_logic; i1: in std_logic;i1: in std_logic; s: in std_logic;s: in std_logic; o: out std_logic);o: out std_logic); END component;END component; signal signal i0, i1, s, o: std_logic;i0, i1, s, o: std_logic;

beginbeginU_mux: muxU_mux: muxport map ( i0 =>i0, i1=>i1, s=>s, port map ( i0 =>i0, i1=>i1, s=>s, o=> o);o=> o); i0 <= ‘0’,i0 <= ‘0’, ‘ ‘1’ after 50 ns,1’ after 50 ns, ‘ ‘0’ after 100 ns,0’ after 100 ns, ‘ ‘1’ after 150 ns,1’ after 150 ns, ‘ ‘0’ after 200 ns,0’ after 200 ns, ‘ ‘1’ after 250 ns,1’ after 250 ns, ‘ ‘0’ after 300 ns,0’ after 300 ns, ‘ ‘1’ after 350 ns;1’ after 350 ns; i1 <= ‘0’,i1 <= ‘0’, ‘ ‘1’ after 100 ns,1’ after 100 ns, ‘ ‘0’ after 200 ns,0’ after 200 ns, ‘ ‘1’ after 300 ns;1’ after 300 ns; s <= ‘0’,s <= ‘0’, ‘ ‘1’ after 200 ns;1’ after 200 ns;end test;end test;

FINITE STATE FINITE STATE MACHINESMACHINES

State0

State1

a=1

a=0

a=1

a=0

FINITE STATE MACHINE FINITE STATE MACHINE IMPLEMENTATIONIMPLEMENTATION

COMBINATIONAL LOGIC

Q

QSET

CLR

D

Q

QSET

CLR

D

...

STATE MEMORY

OUTPUT LOGIC

CLK

INPUTS

PREVIOUS STATE

NEXT STATE

OUTPUTS

(MEALY ONLY)

Mealy machines (1/3)Mealy machines (1/3)

ENTITY fsm is

port(clk, rst_n, a, b: in std_logic;

o: out std_logic);

END ENTITY fsm;

ARCHITECTURE rtl of fsm is

Type state is (state0, state1);

Signal state_pr, state_nx: state;

Mealy machines (2/4)Mealy machines (2/4)BEGINBEGINProcess(clk, rst_n) --sequential partProcess(clk, rst_n) --sequential partbeginbegin if (rst_n=‘0’) thenif (rst_n=‘0’) then state_pr <= state0; --default statestate_pr <= state0; --default state elsif rising_edge(clk) thenelsif rising_edge(clk) then state_pr <= state_nx;state_pr <= state_nx; end if;end if;end process;end process;

Mealy machines (3/4)Mealy machines (3/4)

process(a, state_pr) --combinational partprocess(a, state_pr) --combinational partbeginbegin CASE state_pr isCASE state_pr is WHEN state0 =>WHEN state0 => if (a = ‘1’) thenif (a = ‘1’) then state_nx <= state1;state_nx <= state1; output <= <value>;output <= <value>; elseelse state_nx <= state0; --optionalstate_nx <= state0; --optional output <= <value>;output <= <value>; end if;end if;

Mealy machines (4/4)Mealy machines (4/4)WHEN state1 =>WHEN state1 => if (a = ‘1’) thenif (a = ‘1’) then state_nx <= state0;state_nx <= state0; output <= <value>; --Mealy machineoutput <= <value>; --Mealy machine elseelse state_nx <= state1; --optionalstate_nx <= state1; --optional output <= <value>; --Mealy machineoutput <= <value>; --Mealy machine end if;end if;end CASE;end CASE;end process;end process;

Moore machinesMoore machines

process(a, state_pr) --combinational partprocess(a, state_pr) --combinational partbeginbegin CASE state_pr isCASE state_pr is WHEN state0 =>WHEN state0 => output <= <value>; --Moore machineoutput <= <value>; --Moore machine if (a = ‘1’) thenif (a = ‘1’) then state_nx <= state1;state_nx <= state1; elseelse state_nx <= state0; --optionalstate_nx <= state0; --optional end if;end if;

MOORE MACHINESMOORE MACHINESWHEN state1 =>WHEN state1 => output <= <value>; --Moore machineoutput <= <value>; --Moore machine if (a = ‘1’) thenif (a = ‘1’) then state_nx <= state0;state_nx <= state0; elseelse state_nx <= state1; --optionalstate_nx <= state1; --optional end if;end if;end CASE;end CASE;end process;end process;

EXAMPLE: OUT-OF-EXAMPLE: OUT-OF-SEQUENCE COUNTERSEQUENCE COUNTER DESCRIBE A COUNTER WITH THE DESCRIBE A COUNTER WITH THE

FOLLOWING SEQUENCE:FOLLOWING SEQUENCE:– ““000” => “010” => “011” => 000” => “010” => “011” =>

“001” => “111” => “000”“001” => “111” => “000”

VariablesVariables variable variable variable_name: variable_name: variable_typevariable_type variable_name := variable_valuevariable_name := variable_value Examples:Examples:

– variablevariable x: integer range 0 to x: integer range 0 to 77;;– Variable count: std_logic_vector(3 downto Variable count: std_logic_vector(3 downto

0)0)– x := 2;x := 2;– count := “1110”;count := “1110”;

Signals vs. variablesSignals vs. variables Signal: Signal:

– can be used anywherecan be used anywhere– represents circuit interconnectrepresents circuit interconnect– value is updated at the end of processvalue is updated at the end of process

Variable: Variable: – only in sequential code (process, function, only in sequential code (process, function,

procedure)procedure)– Represents local informationRepresents local information– value is updated immediatelyvalue is updated immediately

PACKAGESPACKAGES Used for declaring global Used for declaring global

constants and functionsconstants and functions Package must be declared in the Package must be declared in the

include libraries before the entity include libraries before the entity declarationdeclaration

PACKAGE EXAMPLEPACKAGE EXAMPLE

PACKAGE tsu_pkg is

CONSTANT word_length: integer := 32; --processor word length

CONSTANT thid_length: integer := 16; --thread id length

CONSTANT cntx_length: integer := 0; --context length

CONSTANT nof_ready_count: integer:= 8; --# ready counts

TYPE sync_data_type is ARRAY (nof_ready_count downto 0) of std_logic_vector(word_length-1 downto 0);

function LOG (X : integer) return integer; --logarithm base 2

end package;

Using a packageUsing a package Package must be declared in the Package must be declared in the

include libraries before the entity include libraries before the entity declarationdeclaration

Library work;Library work;Use work.tsu_pkg.all;Use work.tsu_pkg.all;

Entity …Entity …

GenericsGenerics An alternative way of declaring An alternative way of declaring

parameters, valid only for a single parameters, valid only for a single entity.entity.

ENTITY counter isENTITY counter isGENERIC (wordlength: integer:= 8);GENERIC (wordlength: integer:= 8);PORT (clk, rst_n, en: in std_logic; PORT (clk, rst_n, en: in std_logic;

count: out std_logic_vector(wordlength-1 downto 0)count: out std_logic_vector(wordlength-1 downto 0)););

END counter;END counter;

FUNCTIONSFUNCTIONSPACKAGE body tsu_pkg is function LOG (X : integer) return integer is variable i: integer range 0 to pe_num; variable modulus, modulus_copy: integer range 0 to pe_num; variable remainder, remainder_detect: integer range 0 to 1; variable result: integer range 0 to 20:=0; begin modulus := X; while modulus > 0 loop modulus_copy := modulus; modulus := modulus/2; remainder := modulus_copy rem 2; if modulus >= 1 then if remainder = 1 then remainder_detect := 1; else remainder_detect := remainder_detect; end if; else remainder_detect := remainder_detect; end if; if modulus >= 1 then result := result +1; elsif remainder_detect > 0 then result := result + 1; end if; end loop; return result; end function;

end;

Arithmetic conversion Arithmetic conversion functionsfunctions

Need to include std_logic_arith libraryNeed to include std_logic_arith library Conv_integer: converts a Conv_integer: converts a

std_logic_vector to integerstd_logic_vector to integer– i <= conv_integer(‘0’ & count);i <= conv_integer(‘0’ & count);

Std_logic_vector: converts an integer Std_logic_vector: converts an integer to std_logic_vectorto std_logic_vector– count <= std_logic_vector(i, count’length);count <= std_logic_vector(i, count’length);

ROM entityROM entityentity rominfr isport (clk : in std_logic;en : in std_logic;addr : in std_logic_vector(4 downto 0);data : out std_logic_vector(3 downto 0));end rominfr;

ROM architectureROM architecturearchitecture syn of rominfr istype rom_type is array (31 downto 0) of std_logic_vector (3 downto 0);constant ROM : rom_type :=("0001","0010","0011","0100","0101","0110","0111","1000","1001“,"1010","1

011","1100","1101","1110","1111","0001","0010","0011","0100","0101","0110","0111","1000","1001","1010","1011","1100","1101","1110","1111");

beginprocess (clk)begin if (clk’event and clk = ’1’) then if (en = ’1’) then data <= ROM(conv_integer(addr); end if; end if;end process;end syn;

DUAL –PORT RAM DUAL –PORT RAM ENTITYENTITY

entity rams_14 isentity rams_14 isport (port ( clk : in std_logic;clk : in std_logic; ena : in std_logic;ena : in std_logic; enb : in std_logic;enb : in std_logic; wea : in std_logic;wea : in std_logic; addra : in std_logic_vector(log(addra : in std_logic_vector(log(ramram_depth)-1 downto 0);_depth)-1 downto 0); addrb : in std_logic_vector(log(addrb : in std_logic_vector(log(ramram_depth)-1 downto 0);_depth)-1 downto 0); dia : in std_logic_vector(word_length-1 downto 0);dia : in std_logic_vector(word_length-1 downto 0); doa : out std_logic_vector(word_length-1 downto 0);doa : out std_logic_vector(word_length-1 downto 0); dob : out std_logic_vector(word_length-1 downto 0));dob : out std_logic_vector(word_length-1 downto 0));end rams_14;end rams_14;

DUAL –PORT RAM DUAL –PORT RAM ARCHITECTUREARCHITECTURE

architecture syn of rams_14 isarchitecture syn of rams_14 is type ram_type is array (type ram_type is array (ramram_depth-1 downto 0) _depth-1 downto 0)

of std_logic_vector(word_length-1 downto 0);of std_logic_vector(word_length-1 downto 0); signal RAM : ram_type;signal RAM : ram_type; signal read_addra : signal read_addra :

std_logic_vector(log(std_logic_vector(log(ramram_depth)-1 downto 0);_depth)-1 downto 0); signal read_addrb : signal read_addrb :

std_logic_vector(log(std_logic_vector(log(ramram_depth)-1 downto 0);_depth)-1 downto 0);beginbegin

DUAL–PORT RAM DUAL–PORT RAM ARCHITECTUREARCHITECTURE

process (clk)process (clk) beginbegin if (clk'event and clk = '1') thenif (clk'event and clk = '1') then if (ena = '1') thenif (ena = '1') then if (wea = '1') thenif (wea = '1') then RAM (conv_integer(addra)) <= dia;RAM (conv_integer(addra)) <= dia; end if;end if; read_addra <= addra;read_addra <= addra; end if;end if; if (enb = '1') thenif (enb = '1') then read_addrb <= addrb;read_addrb <= addrb; end if;end if; end if;end if; end process;end process; doa <= RAM(conv_integer(read_addra));doa <= RAM(conv_integer(read_addra)); dob <= RAM(conv_integer(read_addrb));dob <= RAM(conv_integer(read_addrb));end syn;end syn;

AttributesAttributes Data attributes(all synthesizable)Data attributes(all synthesizable)

– d’LOW d’LOW --returns lower index--returns lower index– d’HIGHd’HIGH --returns higher index--returns higher index– d’LEFT d’LEFT --returns leftmost index--returns leftmost index– d’RIGHTd’RIGHT --returns rightmost index--returns rightmost index– d’LENGTH d’LENGTH --returns vector size--returns vector size– d’RANGEd’RANGE --returns vector range--returns vector range– d’REVERSE_RANGEd’REVERSE_RANGE --returns reverse vector range --returns reverse vector range

Signal attributes(first two synthesizable)Signal attributes(first two synthesizable)– s’EVENTs’EVENT --returns true when event on s--returns true when event on s– s’STABLEs’STABLE --returns true when no event on s--returns true when no event on s– s’ACTIVEs’ACTIVE --returns true when s=‘1’--returns true when s=‘1’– s’QUIETs’QUIET <time><time> --returns true when no event on s for --returns true when no event on s for

specified timespecified time– s’LAST_EVENTs’LAST_EVENT --returns time since last event on s--returns time since last event on s– s’LAST_ACTIVEs’LAST_ACTIVE --returns time since s = ‘1’--returns time since s = ‘1’– s’LAST_VALUEs’LAST_VALUE --returns value of s before last event--returns value of s before last event

Common VHDL Common VHDL PitfallsPitfalls

Name inconsistencyName inconsistency Compile: errorCompile: error Severity: TrivialSeverity: Trivial

Reading an outputReading an output Compile: Error: cannot read outputCompile: Error: cannot read output Solution: Use internal signalSolution: Use internal signal

ENTITY counter isENTITY counter is PORT(clk, rst_n: in std_logic;PORT(clk, rst_n: in std_logic; count: out std_logic_vector(3 downto 0));count: out std_logic_vector(3 downto 0));end counter;end counter;Architecture rtl of count isArchitecture rtl of count isbeginbeginPROCESS(clk)PROCESS(clk)beginbegin if clk’event and clk=‘1’ thenif clk’event and clk=‘1’ then if rst_n = ‘0’ then –-synchronous resetif rst_n = ‘0’ then –-synchronous reset count <= (others => ‘0’);count <= (others => ‘0’); elseelse if en = ‘1’ then --count enableif en = ‘1’ then --count enable count <= count + ‘1’; --cannot read output errorcount <= count + ‘1’; --cannot read output error end if;end if; end if;end if; end if;end if;end process;end process;

Multiple unconditional Multiple unconditional concurrent concurrent assignmentsassignments Simulation: ‘X’ valueSimulation: ‘X’ value

Synthesis: ERROR: signal is multiply drivenSynthesis: ERROR: signal is multiply driven Severity: SeriousSeverity: SeriousArchitecture rtl of my_entity is

BEGIN

output <= a AND b;

...

output <= b XOR c;

Process (b,c)

Begin

output <= b OR c;

End process;

End;

Incomplete sensitivity Incomplete sensitivity list list

Simulation: Unexpected behaviorSimulation: Unexpected behavior Synthesis: Warning: Incomplete sensitivity listSynthesis: Warning: Incomplete sensitivity list Severity: SeriousSeverity: Serious Solution: complete sensitivity listSolution: complete sensitivity list

PROCESSPROCESS(a, b)(a, b)BEGINBEGIN d <= (a d <= (a AND AND b) b) OR OR c; --c is missing from sensitivity list!!!c; --c is missing from sensitivity list!!!END PROCESS;END PROCESS;

Not assigning all Not assigning all outputs in outputs in combinational processcombinational process Simulation: Simulation: Synthesis: Warning: Signal not always assigned, storage Synthesis: Warning: Signal not always assigned, storage

may be neededmay be needed Severity: SeriousSeverity: Serious Solution: assign all signalsSolution: assign all signals

PROCESSPROCESS(a, b, c)(a, b, c)BEGINBEGIN if c = ‘0’ thenif c = ‘0’ then d <= (a d <= (a AND AND b) b) OR OR c; --d assigned only first time, c; --d assigned only first time, else else e <= a; --e assigned only second time!!! e <= a; --e assigned only second time!!!

END PROCESS;END PROCESS;

Unassigned signalsUnassigned signals Simulation: Undefined value (‘U’)Simulation: Undefined value (‘U’) Synthesis: Warning: Signal is Synthesis: Warning: Signal is

never used/never assigned a valuenever used/never assigned a value Severity: ModerateSeverity: ModerateArchitecture rtl of my_entity is

Signal s: std_logic;

Begin

Output <= input1 and input2; --s never assigned

End;

Output not assigned or Output not assigned or not connectednot connected Simulation: UndefinedSimulation: Undefined Synthesis: Error: All logic Synthesis: Error: All logic

removed from the designremoved from the design Severity: SeriousSeverity: Serious

ENTITY my_entity IS PORT (input1, input2: in std_logic; output: out std_logic);End my_entity;Architecture rtl of my_entity isSignal s: std_logic;Begins <= input1 and input2; --output never assignedEnd;

Using sequential Using sequential instead of concurrent instead of concurrent processprocess Simulation: Unexpectedly delayed Simulation: Unexpectedly delayed

signalssignals Synthesis: More FFs than Synthesis: More FFs than

expectedexpected