Unit 8Unit 8Combinational Circuit Combinational Circuit Design and Simulation Design and Simulation

Using GatesUsing Gates

Ku-Yaw ChangKu-Yaw Changcanseco@mail.dyu.edu.twcanseco@mail.dyu.edu.tw

Assistant Professor, Department of Assistant Professor, Department of Computer Science and Information EngineeringComputer Science and Information Engineering

Da-Yeh UniversityDa-Yeh University

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ContentsContents

8.18.1 Review of Combinational Circuit DesignReview of Combinational Circuit Design

8.28.2 Design Circuits with Limited Gate Fan-InDesign Circuits with Limited Gate Fan-In

8.38.3 Gate Delays and Timing DiagramsGate Delays and Timing Diagrams

8.48.4 Hazards in Combinational LogicHazards in Combinational Logic

8.58.5 Simulation and Testing of Logic CircuitsSimulation and Testing of Logic Circuits

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Propagation DelayPropagation Delay

In nanoseconds

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Timing DiagramTiming Diagram

Frequently used in the analysis of sequential Frequently used in the analysis of sequential circuitscircuits

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Timing Diagram With DelayTiming Diagram With Delay

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ContentsContents

8.18.1 Review of Combinational Circuit DesignReview of Combinational Circuit Design

8.28.2 Design Circuits with Limited Gate Fan-InDesign Circuits with Limited Gate Fan-In

8.38.3 Gate Delays and Timing DiagramsGate Delays and Timing Diagrams

8.48.4 Hazards in Combinational LogicHazards in Combinational Logic

8.58.5 Simulation and Testing of Logic CircuitsSimulation and Testing of Logic Circuits

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HazardsHazards

When the input to a combinational circuit When the input to a combinational circuit changes, unwanted switching transients changes, unwanted switching transients may appear in the output.may appear in the output. Different pathsDifferent paths Different propagation delaysDifferent propagation delays

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Types of HazardsTypes of Hazards

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A Static 1-hazardA Static 1-hazard

A = C = 1A = C = 1 F = AB’ + BC = B + B’ = 1F = AB’ + BC = B + B’ = 1 F should remain a constant 1 when B changes F should remain a constant 1 when B changes

from 1 to 0.from 1 to 0.

AssumptionAssumption A propagation delayA propagation delay

of 10 nsof 10 ns

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A Static 1-hazardA Static 1-hazard

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Hazard DetectionHazard Detection

Write down the sum-of-products expression for Write down the sum-of-products expression for the circuit.the circuit.

Plot each term on the map and loop it.Plot each term on the map and loop it.

If any two adjacent 1’s are not covered by the If any two adjacent 1’s are not covered by the same loop, a 1-hazard exists for the transition same loop, a 1-hazard exists for the transition between the two 1’s.between the two 1’s.

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Hazard RemovalHazard Removal

Add a loop on the Karnaugh mapAdd a loop on the Karnaugh map Corresponding gateCorresponding gate

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0-hazards0-hazards

Product of sumsProduct of sums F = (A+C)(A’+D’)(B’+C’+D)F = (A+C)(A’+D’)(B’+C’+D)

Four pairs of adjacent 0’s Four pairs of adjacent 0’s that are not covered by a that are not covered by a common loopcommon loop Each corresponds to a 0-Each corresponds to a 0-

hazardhazard

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0-hazards0-hazards

=0

=0 =1

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Removing HazardsRemoving Hazards

Eliminate the 0-hazardsEliminate the 0-hazards F=(A+C)(A’+D’)(B’+C’+D)F=(A+C)(A’+D’)(B’+C’+D)(C+D’)(A+B’+D)(C+D’)(A+B’+D)

(A’+B’+C’)(A’+B’+C’)

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ContentsContents

8.18.1 Review of Combinational Circuit DesignReview of Combinational Circuit Design

8.28.2 Design Circuits with Limited Gate Fan-InDesign Circuits with Limited Gate Fan-In

8.38.3 Gate Delays and Timing DiagramsGate Delays and Timing Diagrams

8.48.4 Hazards in Combinational LogicHazards in Combinational Logic

8.58.5 Simulation and Testing of Logic CircuitsSimulation and Testing of Logic Circuits

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VerificationVerification

Building a circuitBuilding a circuit

Simulating a circuit on a computerSimulating a circuit on a computer EasierEasier FasterFaster More economicalMore economical

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Simulation StepsSimulation Steps

First, specify the circuit component and First, specify the circuit component and connectionsconnections

Second, specify the circuit inputsSecond, specify the circuit inputs

Finally, observe the circuit outputsFinally, observe the circuit outputs

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SimulationSimulation

Two logic values, 0 and 1, are not Two logic values, 0 and 1, are not sufficientsufficient A gate input or output maybe unknownA gate input or output maybe unknown

Represented by XRepresented by X An open circuit, or high impedance (hi-Z)An open circuit, or high impedance (hi-Z)

Represented by ZRepresented by Z

Four-value logic simulatorFour-value logic simulator 0, 1, X, Z0, 1, X, Z

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SimulationSimulation

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Possible CausesPossible Causes

SimulationSimulation Incorrect designIncorrect design Gates connected wrongGates connected wrong Wrong input signals to the circuitWrong input signals to the circuit

Built in labBuilt in lab Defective gatesDefective gates Defective connecting wiresDefective connecting wires

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Incorrect OutputIncorrect Output

F = AB(C’D+CD’) + A’B’(C+D)F = AB(C’D+CD’) + A’B’(C+D) A=B=C=D=1A=B=C=D=1

The output F has the wrong valueThe output F has the wrong value

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Homework #2Homework #2

1.1. 8.18.1

2.2. 8.28.2

3.3. 8.38.3

4.4. 8.48.4

5.5. 8.58.5

Paper Submission, due on April 1, 2004.Late submission will not be accepted.