Post on 03-Apr-2018
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Power aware embedded
systemsR.Prabakaran
Center for Convergence of Technologies
Anna University
Tiruchirappalli
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Need for Power Management
Current scenario
Mobile Phone - 1 to 3 Hrs active time
Laptop - 1.30 to 2 Hrs active time
MP3 Players - 8 to 12 Hrs
MPEG 4 Players - 3-6 Hrs
Hence, reducing power consumption has become a majorchallenge in the design and operation of todays Portableand Handheld Embedded devices
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Moores LawIn 1965, Intels Gordon
Moore predicted that thenumber of transistors
that can be integrated on
single chip woulddouble about every two
years
feature size&
die size
Dual Core
Itanium with1.7B transistors
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Intel 4004 Microprocessor1971
0.2 MHz clock
3 mm2 die
10,000 nm feature size
~2,300 transistors
2mW power
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Intel Pentium (IV) Microprocessor2001
1.7 GHz clock
271 mm2 die
180 nm feature size
~42M transistors
64W power
30 (15*2) years
8500x faster
90x bigger die
55x smaller feature size
18,000x more Ts
32,000x (215)more
power
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Power and Energy
Power is the rate at which the systems does
the work
P= W/T
Energy is the amount of work a systems
perform over a period of time
E=PT
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Static Vs Dynamic Power
Consumption Static Power mode the processor consume
the same amount of power for all
applications
In Dynamic Power consumption the
processor will consume power based on its
application
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Dynamic Power Consumption
Pdynamic aCV2f .
V- supply voltage
f- frequency C- physical capacitance
a-Activity factor(0 1 or 1 0)
~~
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Cause for Dynamic Power
Consumption Switched capacitance
Short-circuit current
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Classification Of DPM
Reduce the physical capacitance or storedelectrical charge of a circuit.
Lower dynamic power is to reduce theswitching activity.
Reduce dynamic power consumption is to
reduce the clock frequency. Reduce dynamic power consumption is toreduce the supply voltage
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Leakage current in transistor
Reverse-biased-junction leakage
Gate-induced-drain leakage
Sub threshold leakage
Gate-oxide leakage
Gate-current leakage and Punch-through leakage.
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Various Ways to Reduce the Power
Circuit And Logic Level Techniques
Low-Power Interconnect
Low-Power Memories and Memory Hierarchies
Low-Power Processor Architecture Adaptations
Dynamic Voltage Scaling
Resource Hibernation
Compiler-Level Power Management Application-Level Power Management
Cross-Layer Adaptations
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Circuit And Logic Level Techniques
Transistor Sizing.
Transistor Reordering.
Half Frequency and Half Swing Clocks.
Logic Gate Restructuring.
Technology Mapping
Low Power Flip Flops Delay-Based Dynamic-Supply Voltage Adjustment
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Low-Power Interconnect
Bus Encoding And CrossTalk.
Low Swing Buses.
Bus Segmentation.
Network-On-Chip
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Low-Power Memories and Memory
Hierarchies Splitting Memories Into Smaller
Subsystems.
Augmenting the Memory Hierarchy WithSpecialized Cache Structures.
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Low-Power Processor Architecture
Adaptations Adaptive Caches.
Adaptive Instruction Queues.
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Dynamic Voltage Scaling
Unpredictable Nature Of Workloads.
Indeterminism And Anomalies In Real
Systems.
Interval-Based Approaches.
Intertask Approaches.
Intratask Approaches
The Implications of Memory Bounded Code.
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Dynamic Voltage Frequency Scaling
The combination of scaling the supply
voltage and clock frequency in tandem is
called dynamic voltage scaling(DVS).
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Architectural Overview
USER/ APPLICATION
SPACE
OS KERNEL
DPM
POLICY MANAGER
POLICIES
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Resource Hibernation
Disk Drives.
Network Interfaces.
Displays.
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Compiler-Level Power Management
Remote Compilation and Remote Execution
The Limitations of Statically Optimizing
Compilers.
Dynamic Compilation.
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Application-Level Power
Management Application Transformations and
Adaptations
Application Hints.
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Cross-Layer Adaptations
This approaches gives the very effective
power management . It adopt OS Level,
Compiler level as well as middleware levelapproach to solve the power need of the
entire system
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The Commercial Support
The Pentium M Processor.
The Intel PXA27x Processors.
The Transmeta Crusoe Processor.
IBM Dynamic Power Management.
Powerwise and Intelligent Energy
Management (ARM)
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Research Labs
IBM Research Lab
USC Information Sciences Institute
Computer Architecture andPower Aware Systems Research Group ,BINGHAMTON UNIVERSITY
Lattice Semiconductor Transmeta Research Lab
Intel Research Lab