Energy-Aware Computing: Low-Power Circuit Techniquesperla/ugrad/EAC/EAC2.pdf · Energy-Aware...
Transcript of Energy-Aware Computing: Low-Power Circuit Techniquesperla/ugrad/EAC/EAC2.pdf · Energy-Aware...
Energy-Aware Computing: Low-Power Circuit Techniques, 2017 Page 1
Computer Science and EngineeringChalmers University of Technology
Energy-Aware Computing: Low-Power Circuit Techniques
Per Larsson-Edefors
Energy-Aware Computing: Low-Power Circuit Techniques, 2017 Page 2
• In previous lectures, we’ve seen two distinct mechanisms causing power to be dissipated:– Dynamic - switching.– Static - subthreshold.
• Important to note that both mechanisms benefit more than linearly from reduced VDD.
Two Mechanisms of Power DissipationPsw = Pleak
Pleak simulated, Psw extrapolated from 1.2 V.
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Common Low-Power Circuit Techniques
• Body biasing • Multi-VT
• Multi-VDD
• DVFS• Clock gating• Power gating
• But beside the above techniques, designers always strive to make systems power efficient at all levels, e.g., by – minimizing switched capacitance.– balancing IC technology used and performance needs.
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Best Design Practice for Power Reductions
• Priority on Psw (Pleak requires more invasive solutions).• Consider Psw = f C VDD
2. Broadly, implementation decisions to reduce Psw via …– f and VDD are system wide and need to be
negotiated early on in a project.– the switched capacitance (C) can be handled
at later implementation stages, at RTL and gate level (slide 18 previous lecture).
• Approximate computing: Inspired by SNR-guided DSP implementation, adjust data precision to application needs.
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Technology Flavors
• Select adequate IC technology.– Main question: How powerful need the transistors be
in terms of current delivery ION ? Powerful power dissipating!• Different flavors:
– Low power (LP) with higher VTs.– High performance (in our case, GP) with lower VTs and
more aggressive design rules.• Each flavor has got different VT options:
– Low VT (LVT), Standard VT (SVT), High VT (HVT).– LP_LVT: 0.40-0.49 V.– GP_LVT: 0.25-0.36 V (slide 27 of my previous lecture).
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Technologies via CMP – our IC Broker
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A Smorgasbord of IC Options
• Technology options + EDA tool supportDifferent low-power techniques supported.
Source: UMC
Source: UMC
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• The MOSFET actually has four terminals, not three (gate, drain and source).
• The fourth is called body.• In Isub e-VT, VT depends
on MOSFET terminal voltages:
The MOSFET Body Terminal
Source: USC
Body electrode
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• In an NMOSFET,VT decreases with an increasing body voltage (VB).– For FinFETs from previous lecture,
back biasing does not work well.– For Fully Depleted-Silicon on Insulator
(FD-SOI), thin BOX (buried oxide) allows for back bias control.
Low-Power Technique 1: Body Biasing
VB
0 1
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• Reverse body biasing (RBB): VB < 0 V (NMOSFET) VT increases. leakage decreases.
• Forward body biasing (FBB): VB > 0 V (NMOSFET) VT decreases. higher speed.
Reverse and Forward Body Biasing
• Remember variations?• Body bias allows for tuning
at fab: Performance and power binning…
Source: ABB’02
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Fully Depleted-Silicon on Insulator (FD-SOI)
• FD-SOI and FinFET; the main alternatives for scaled CMOS:– FD-SOI mainly for low power;
good body bias control.– FinFET mainly for high speed;
limited leakage control.
BOX
Source: STM
FD-SOI: 1-V VB change 85-mV VT change
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• Logic paths exhibit different delays. • Critical paths must satisfy clock rate constraint
implementation must ensure gates are fast enough.• But what about the fast paths … can their
intrinsic speed be converted to power reductions?
Delay Distribution of Logic
Source: LPDE’09/Ch 4
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• Assign slow transistors to fast paths (makes these slower) use transistors with high VT Pleak is reduced (but Psw more or less unchanged).
Low-Power Technique 2: Multi-VT
Source: LPDE’09/Ch 4
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• First order delay 1/VDD and Psw VDD2:
– Reduce VDD for circuits that are not timing critical both Psw and Pleak are reduced.
– Optimal number of VDD levels? Consider infrastructure overheads like voltage generation.
Match VDD to Performance Need
Source: LPDE’09/Ch 4
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Low-Power Technique 3: Multi-VDD
Dual- VDD ALU example from LPDE’09/Ch 4
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System-on-Chips (SoCs) with Several VDDs
Source: SynopsysSource: IEEE SOLID-STATE CIRCUITS MAGAZINE
Steadily improving on-chip voltage converters.
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SoC Implementation Challenges
• Multiple VDDs– makes implementation and verification more complex.– requires different voltages; how are they generated?– requires voltage-level conversions between domains,
which creates an overhead. • What about synchronization and timing
between blocks?– Domains may have different clock rates.– Domains may have varying clock rates.
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Planning Supply Voltages
• Overall, use minimal VDD to limit power dissipation. – High performance low VT.– Low standby power high VT.
• To simplify integration, logic and memory should operate under the same VDD. However, logic and memory have very different VDD - VT tradeoffs:– Unused SRAM portions are leaking
ought to use high VT + low VDD to reduce standby power (otherwise very significant in huge memories).
– However, due to read disturb and write failures, high VT + low VDD spells big problems for SRAM cells.
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• Timing slack can be used for power reductions: Dynamic Voltage and Frequency Scaling (DVFS).
Low-Power Technique 4: DVFS
Read more in CATPE’08/Ch 3
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• Conventional DVFS: Predefined performance states, controlled by OS slow transitions.
• Intel’s Speed Shift succeeded Speed Step in 2015: CPU handles transitions (faster); OS to relinquish (some) control.– Main gain is performance, not so much power dissipation.
Faster DVFS State Transitions
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• Aggressive VDD reduction would cause timing violations and, thus, computation errors.
• Solution: Implement a feedback system that regulates speed, in the process also handling variations.
Circuit Adaptation for DVFS
Read more in CATPE’08/Ch 3.5
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Clock arrival times are hard to synchronize. Such static variations are handled as a side effect.
Example on Variations
Source: POWER’11
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• High clock rates or extremely compute-intensive code can expose timing issues.
Detection of Timing Failures
Source: ARM’11
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Clock Tree Design
Source: ST Microelectronics
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Low-Power Technique 5: Clock Gating
Source: LPDE’09/Ch 8
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Recap: Low-Power Techniques
• Body biasing
• Multi-VT
• Multi-VDD
• DVFS
• Clock gating
• Power gating
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Low-Power Technique 6: Power Gating
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Power Gating of Execution Unit
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• Need IC cell library support to implement power gating:– Level shifters, isolation
level shifters, isolation cells, always-on buffers and inverters, retention cells, and power switches.
• EDA tool must support transition control:– Trade off between rush
current and wake-up time.
Power Gating after Place&Route
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Power Gating Impacts Area Significantly
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Identify Multiply Activity
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Limited Mult Utilization Allows for Savings
Benchmark: EEMBC Autocorrelation
Benchmark: EEMBC FFT
• Limited multiply activity, early in application multiplier can be power gated since it becomes idle.
• Trade off: Static power reductions during idle vs power overhead for power gating.
More extensive multiply activity.
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Low-Power Options – Pros and Cons
Source: Cadence
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• Early design decisions yield higher power reductions than late decisions.– Decisions based on
holistic view even better.– Co-optimization across
levels is complex; depends on EDA tool support.
• System architects should be aware of what low-power techniques exist.
Power Reductions in Design Flow
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• Low-power techniques clearly exist. But how do we make use of them in complex systems?
• Designer’s competence + IP/cell infrastructure + EDA tools.
Missed Opportunities?
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Industry View on Low-Power Techniques
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Conclusion
• Reducing circuit power dissipation is done by using best design practices and by employing a few well known low-power techniques.
• Support from EDA (CAD) tools and IC technology (cell libraries) is essential to handle low-power design in an efficient manner.
• Common to all techniques is that reducing VDDis effective for reducing power.
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References• ABB’02: “Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die
Parameter Variations on Microprocessor Frequency and Leakage”, J. Tschanz et al., IEEE JSSC, Nov. 2002.
• ARM’11: “A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation”, D. Bull et al., IEEE JSSC, 2011.
• CATPE’08: “Computer Architecture Techniques for Power-Efficiency”, S. Kaxiras and M. Martonosi, Morgan & Claypool, 2008.
• LPDE’09: “Low Power Design Essentials”, J. Rabaey, Springer, 2009.• POWER’11: “POWER7™, a Highly Parallel, Scalable Multi-Core High End Server
Processor”, D. F. Wendel et al., IEEE JSSC, 2011.• And many local Chalmers papers.