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PCI 9054RDK-860 Hardware Reference Manual
PCI 9054RDK-860 Hardware Reference Manual
Version 2.3
July 2005
Website: http://www.plxtech.comTechnical Support: http://www.plxtech.com/support/
Phone: 408 774-9060 800 759-3735
Fax: 408 774-2169
© 2005 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Order Number: 9054/860-RDK-HRM-P1-2.3
Printed in the USA, March 2005
Notice This document contains PLX Confidential and Proprietary information. The contents of this document may not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to entirely verify and test all information, in all circumstances, particularly information relating to non-PLX manufactured products. PLX makes neither warranties nor representations relating to the quality, content or adequacy of this information. The information in this document is subject to change without notice. Although every effort has been made to ensure the accuracy of this manual, PLX assumes no responsibility for any errors or omissions in this document. PLX shall not be liable for any errors, incidental or consequential damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of this RDK, or for any damage or loss caused by deletion of data as a result of malfunction or repair.
About This Manual This manual provides information about the PCI 9054RDK-860 Rapid Development Kit (RDK), from a hardware perspective. It contains descriptions of all major functional circuit blocks on the board. This manual also includes the complete schematic and bill of materials.
REVISION HISTORY
Date Version Comments
April 2000 2.0 Hardware Reference Manual release
June 2002 2.1 Updated Bill of Materials, HRM and Schematic
March 2003 2.2 Corrected EEPROM Register Value Tables
July 2005 2.3 Updated EEPROM values
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
i
Table of Contents
1. GENERAL INFORMATION ................................................................................. 1-1
1.1 FEATURES .............................................................................................. 1-1
2. HARDWARE INSTALLATION............................................................................. 2-1
2.1 INSTALLATION PROCEDURE ...................................................................... 2-1 2.2 VERIFY INSTALLATION .............................................................................. 2-1
3. SYSTEM ARCHITECTURE ................................................................................. 3-1
4. HARDWARE ARCHITECTURE........................................................................... 4-1
4.1 HARDWARE MEMORY MAP ....................................................................... 4-1 4.2 MAIN COMPONENTS................................................................................. 4-2
4.2.1 PCI 9054 ................................................................................... 4-2 4.3 MPC860 ................................................................................................ 4-2 4.4 CLOCK.................................................................................................... 4-3
4.4.1 PCI Clock .................................................................................. 4-3 4.4.2 Local Clock ............................................................................... 4-3
4.5 MEMORY................................................................................................. 4-4 4.5.1 Boot ROM (FLASH) .................................................................. 4-4 4.5.2 SDRAM ..................................................................................... 4-4
4.6 SERIAL PORT .......................................................................................... 4-7 4.7 DEBUG PORT .......................................................................................... 4-7 4.8 INTERRUPTS............................................................................................ 4-7
4.8.1 MPC860 Critical Interrupt.......................................................... 4-7 4.8.2 MPC860 External Interrupt........................................................ 4-7 4.8.3 PCI-to-Local interrupt ................................................................ 4-7 4.8.4 PCI Interrupt (INTA#) via the PCI 9054..................................... 4-7
4.9 LED INDICATORS..................................................................................... 4-7 4.10 POWER SUPPLY ...................................................................................... 4-7 4.11 MPC860 PERIPHERALS CONNECTOR (POM2) .......................................... 4-8 4.12 RESET CIRCUITRY ................................................................................... 4-9
4.12.1 Power-On Reset and Pushbutton Reset ................................... 4-9 4.12.2 Register Initialization ................................................................. 4-9 4.12.3 Serial EEPROM Loads............................................................ 4-10
4.13 ARBITRATION ........................................................................................ 4-12 4.14 POWER MANAGEMENT ........................................................................... 4-12 4.15 PROTOTYPE AREA ................................................................................. 4-12 4.16 TEST CONNECTORS............................................................................... 4-12 4.17 TEST POINTS ........................................................................................ 4-12 4.18 JUMPERS AND CONNECTORS SUMMARY .................................................. 4-13
4.18.1 Configuration Jumpers (Resistors).......................................... 4-13 4.18.2 Jumpers, Test Points, and Connectors ................................... 4-14
4.19 SPECIAL CONSIDERATIONS..................................................................... 4-14
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
iii
5. SOFTWARE ARCHITECTURE ........................................................................... 5-1
5.1 PCI SDK.................................................................................................5-1 5.1.1 PLXMon (Uses PCI SDK) ..........................................................5-1 5.1.2 Windows Device Drivers ............................................................5-1
6. SERIAL INTERFACE PINOUT............................................................................ 6-1
6.1 SCC1 .....................................................................................................6-1 6.2 SCC2 .....................................................................................................6-3 6.3 SCC3 .....................................................................................................6-4 6.4 SCC4 .....................................................................................................6-5 6.5 MISC......................................................................................................6-6
7. CUSTOMER SUPPORT ...................................................................................... 7-1
8. REFERENCES .................................................................................................... 8-1
9. BILL OF MATERIALS & SCHEMATICS............................................................. 9-1
LIST OF FIGURES FIGURE 3-1. PCI 9054RDK-860 SYSTEM ARCHITECTURE.................................................3-1 FIGURE 4-1. MPC860 PERIPHERALS CONNECTOR (POM2)...............................................4-8
iv PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
LIST OF TABLES
TABLE 4-1. LOCAL BUS HARDWARE MEMORY MAP ........................................................... 4-1 TABLE 4-2. LONG SERIAL EEPROM LOAD REGISTERS ................................................... 4-10 TABLE 4-3. EXTRA LONG SERIAL EEPROM LOAD REGISTERS ........................................ 4-11 TABLE 4-4. CONFIGURATION JUMPERS (RESISTORS)....................................................... 4-13 TABLE 4-5. JUMPERS, TEST POINTS, AND CONNECTORS ................................................ 4-14 TABLE 6-1. UART.......................................................................................................... 6-1 TABLE 6-2. HDLC CONTROLLER ..................................................................................... 6-1 TABLE 6-3. TRANSPARENT CONTROLLER ......................................................................... 6-1 TABLE 6-4. ETHERNET CONTROLLER ............................................................................... 6-2 TABLE 6-5. I2C............................................................................................................... 6-2 TABLE 6-6. CENTRONIC TRANSMITTER............................................................................. 6-2 TABLE 6-7. UART.......................................................................................................... 6-3 TABLE 6-8. HDLC.......................................................................................................... 6-3 TABLE 6-9. TRANSPARENT CONTROLLER ......................................................................... 6-3 TABLE 6-10. UART........................................................................................................ 6-4 TABLE 6-11. HDLC........................................................................................................ 6-4 TABLE 6-12. TRANSPARENT CONTROLLER ....................................................................... 6-4 TABLE 6-13. UART........................................................................................................ 6-5 TABLE 6-14. HDLC........................................................................................................ 6-5 TABLE 6-15. TRANSPARENT CONTROLLER ....................................................................... 6-5 TABLE 6-16. SI WITH TDM (TIME SLOT ASSIGNOR) .......................................................... 6-6 TABLE 9-1. BOM – COMPONENTS SHOULD BE ASSEMBLED............................................... 9-1 TABLE 9-2. BOM – THROUGH HOLE COMPONENTS........................................................... 9-3 TABLE 9-3. BOM – MANUALLY INSERTED COMPONENTS ................................................... 9-3 TABLE 9-4. BOM – MISCELLANEOUS COMPONENTS.......................................................... 9-3 TABLE 9-5. BOM – COMPONENTS SHOULD NOT BE ASSEMBLED ....................................... 9-3
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
v
1. General Information The PCI 9054RDK-860 Rapid Development Kit enables designers to learn about PCI 9054 features and design issues before implementing their own designs. When used in conjunction with the PCI Software Development Kit, designers can test and evaluate the PCI 9054 device by using the provided sample software. In addition, designers can implement and test software aimed at specific applications. Through the use of this Rapid Development Kit, designs can be brought to market faster and more efficiently.
1.1 Features
The PCI 9054RDK-860 Rapid Development Kit contains a 12.35" L x 4.20" W circuit board, with the following features:
• PCI 9054 (176-pin PQFP)—PCI v2.2 compliant, CompactPCI Hot Swap Friendly, I2O-compatible PCI I/O accelerator
• Motorola MPC860—32-bit RISC-embedded processor • 32 MB SDRAM memory • 512 KB FLASH memory • One external serial RS-232 port, using SCC1 of the MPC860 • Reset switch • MPC860 JTAG port (6-pin) connector • MPC860 development port (2x5 pin) connector • Debug LED • Prototype area • POM2 interface connector for MPC860 peripheral devices • Debug headers
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
1-1
2. Hardware Installation
2.1 Installation Procedure
Use the following procedure to prevent electrostatic damage to the host computer and to the circuit board while installing the PCI 9054RDK-860 circuit board.
To install the PCI 9054RDK-860 circuit board 1. Log off and shut down the host computer.
2. Turn off power to the computer and disconnect the power cord. Ensure that the chassis and antistatic bag which holds the PCI 9054RDK-860 circuit board are properly grounded, preferably at an antistatic workstation with wrist straps.
3. Ground yourself by touching the computer case.
4. Remove the computer cover.
5. Remove the PCI 9054RDK-860 circuit board from the antistatic bag and place it into an empty PCI slot.
6. Secure the captive screw to ensure proper electrical grounding and mechanical stability.
2.2 Verify Installation
After installation, verify that the PCI 9054RDK-860 circuit board is correctly installed.
To verify that the circuit board is correctly installed 1. Install the PCI SDK (Software Design Kit) onto the computer. Refer to PCI SDK User’s
Manual for software installation.
2. Double click the PLXMon icon (located in the C:\PCI SDK folder).
3. When the PLXMon application starts, it should select the PCI 9054RDK-860 as default. If the verification is not successful, confirm the hardware is correctly installed, and then reinstall all software.
4. If necessary, contact Customer Support for further assistance (refer to the section, “Customer Support,” for information on how to contact PLX).
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
2-1
3. System Architecture The purpose of this RDK is to demonstrate the following:
• Connection between the PCI 9054 and MPC860 • Host CPU accesses to all Local resources • Local CPU (MPC860) accesses to all PCI resources • Additional features to demonstrate I2O operations
The PCI 9054RDK-860 features:
• PCI 9054 (PCI Bus Master/Slave Interface chip) • MPC860 (PowerPC CPU with communications processor) • Boot ROM (FLASH) • Memory subsystem (SDRAM) • Debug port (serial port, MPC860 JTAG, and MPC860 development port) • MPC860 peripheral port connector
PCI 9054
Local Bus
PCI Bus
SDRAM(32 MB)
FLASH (512 KB)MPC860
MPC860Peripherals
SerialPort
Figure 3-1. PCI 9054RDK-860 System Architecture
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
3-1
Section 3 System Architecture
The MPC860 has Read/Write access to the following:
• SDRAM • FLASH • MPC860 peripherals • Serial port • PCI 9054 internal registers (including DMA registers) • PCI Bus devices [using the Direct Master (DM) Memory Read and Write, I/O Read and Write, or Configuration Cycle 0 and 1 generation through the PCI 9054]
Any PCI Bus Master device has access to all PCI 9054 internal registers and PCI-to-Local Memory and I/O spaces [(Direct Slave (DS) access)]. PCI Bus Master devices by way of the DS access can access all MPC860 peripherals, including the serial port, SDRAM, and FLASH.
The PCI 9054 DMA controller is the most efficient way to transfer data between the Local Bus and the PCI Bus. In this case, the PCI 9054 is the Master of both the Local and PCI Buses when transferring data.
The combination of the DM, DS, DMA, interrupt generation on the Local and PCI Buses, and I2O-Ready PCI 9054 architecture enables the PCI 9054RDK-860 to operate as an I2O-compliant system.
In addition, the PCI 9054RDK-860 provides the complete PCI SDK to aid programmers in developing drivers and applications.
3-2 PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
4. Hardware Architecture
4.1 Hardware Memory Map
Table 4-1. Local Bus Hardware Memory Map
Address Range Device Chip
Select Bus
Width Wait
State(s) Comments
FFF7 FFFF FFF0 0000 FLASH CS0# 8 6 FLASH (Boot Code) — controlled by
MPC860 GPCM
FFEF FFFF FF00 0000
Internal Registers and RAM
Internal NA NA MPC860 internal registers (Internal I/O spaces)
FEFF FFFF 8000 0000 Unused
7FFF FFFF 7000 0000 Unused
6FFF FFFF 6000 0000 Unused
5FFF FFFF 5000 0000
DM I/O (PCI 9054) NA 32 NA Direct Master I/O space —controlled by
MPC860 GPCM 4FFF FFFF 4000 0000
DM Memory (PCI 9054) NA 32 NA Direct Master Memory space —
controlled by MPC860 GPCM
3FFF FFFF 3000 0000
PCI 9054 Internal
Registers CS3# 32 5 PCI 9054 internal register space (512
bytes) — controlled by MPC860 GPCM
2FFF FFFF 2000 0000 Unused
1FFF FFFF 1000 0000 Unused
01FF FFFF 0000 1000 SDRAM CS1# 32 5-1-1-1 SDRAM space (32 MB) — controlled by
MPC860 UPM(A)
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
4-1
Section 4 Hardware Architecture
4.2 Main Components
4.2.1 PCI 9054
The PCI 9054 is a PCI Bus Master interface chip (PCI Bus Specification v2.2 compliant) with Direct Slave (DS), Direct Master (DM), two DMA controllers, and an I2O-compliant Messaging Unit. It also is PCI Hot Plug and CompactPCI Hot Swap compliant. It allows for easy interface to the Motorola MPC860, IBM 401XX, and Intel i960XX processor families.
This RDK is configured using the MPC860 MPU M-mode interface. Therefore, J1 pins 3 through 6 should be open. In M mode, glue logic is not required to interface the PCI 9054 to the MPC860.
If the PCI 9054 TEST pin is pulled high (that is, J1 pins 1 and 2 are shorted), all PCI 9054 pins become input (except the USERo pin) and the PCI 9054 operates in NANDTREE Test mode.
In a normal operation, J1 should be open (that is, no jumper blocks).
The serial EEPROM (93LC56B) is used to configure the PCI 9054 during power-on and to hold Vital Product Data (VPD). The power-on configuration serves as PCI Plug-and-Play (PnP), PCI 9054 configuration, Local Bus and board configuration. The serial EEPROM is a 3.3V part; however, a 5V part can also be used, as the PCI 9054 is 5V I/O tolerant.
Although the PCI 9054 has internal 50K-ohm pull-up resistors on the Address Bus and other input pins, RN1 through RN8 were added to pull up the address lines with 10K-ohm resistors. These resistor networks are optional.
The PCI Bus Power Management Event (PME#) signal and internal registers are included in the PCI 9054 to support PCI Bus Power Management features.
The PCI Bus ENUM# and Local Bus LEDon/LEDin pins are included to support the CompactPCI Hot Swap feature. Refer to PCI 9054 Data Book or CompactPCI 9054RDK-860 for CompactPCI RDK.
The PCI 9054 supports a standard Single cycle (one Address phase per one Data phase) and Burst cycle [one Address phase for one or more Data phases, as MPC860 and its peripherals are limited to four longword (Lword) (32 bit) data bursts at a time] to or from the MPC860. In addition, the PCI 9054 supports a Back-Off mechanism through the MPC860 Retry function. When the PCI 9054 detects a possible Deadlock situation, mainly DS and DM occuring simultaneously, the PCI 9054 asserts the RETRY# signal requesting the MPC860 to Back-Off (the DM releases the current cycle for a later time).
The PCI 9054 also supports the MPC860 IDMA transfer to or from the PCI Bus using the MDREQ# signal. MDREQ# (DMA request to the MPC860 IDMA controller) is asserted by the PCI 9054 as long as the DM FIFO space is available. In other words, MDREQ# is de-asserted only when the DM Write FIFO is full. The software must account for MDREQ# being asserted when the IDMA is not ready to transfer data. Refer to PCI 9054 Data Book for more information.
The PCI 9054 has full access to the MPC860 communications and MPC860 memory controller modules. The MPC860 has full access to the PCI 9054 internal registers using the CS3# signal (CS9054# => CCS#) and all PCI resources using the Direct Master Read and Write (DMR and DMW) cycles. Refer to PCI 9054 Data Book for more information.
4.3 MPC860
The Motorola MPC860XX is a 32-bit PowerPC-core-based MPU with a programmable communications processor and built-in memory controller modules. The MPC860 includes the JTAG and development ports connector for debugging purposes. The development port supports many different types of Motorola-approved tools including FRZ signal or VFLS[0:1] signal to pins 1 and 6. Refer to the Motorola website for further details on these tools.
4-2 PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
Section 4 Hardware Architecture
The MPC860 power-on configuration is done while HRESET# is asserted. MODCK[1:2] determines the initial operating frequency, while U34 and the pull up/down resistor network determines the other MPC860 initial operating mode. Any of these power-on configuration settings can be reprogrammed by way of the software after boot up.
Either a 4-MHz or a 50-MHz oscillator is used to generate a reference clock to the MPC860. The MPC860 generates Local Bus Clock Out (CLKOUT) to the clock buffer. In turn, the clock buffer generates all Local Bus clocks, including the PCI 9054 (LCLK), SDRAM (SDRAM_CLK), and PLX Option Module 2 (POM2_CLK) clocks.
Note: Refer to the section, “Clock,” for further design notes.
All MPC860 peripheral signals are connected to the POM2 (PLX Option Module 2) for MPC860 peripheral expansion. Only SSC1 is used as the PLXROM debug connection to the remote terminal. All other peripheral expansion is available to the user.
The GPL(A) ports and BS_A port are used to control the SDRAM. The GPL(A)[0:3] signals are connected to all SDRAM control signals, as well as the external address Mux (U31, U32, and U33). BS_A[0:3] are used as a Read/Write Enable signal. Refer to the section, “SDRAM,” for more information.
One of the MPC860 internal Chip Selects (CS[3:0]#) is used to access the PCI 9054 internal registers (CS3# or CS9054#). CS0# is assigned to access the FLASH (CSFLASH#), while CS1# is used to access the SDRAM (CSSDRAM#).
For exception process, IRQ1# is connected to the PCI 9054 Local Interrupt In/Out pin in addition to the TEA# and the RETRY# signals from the PCI 9054.
4.4 Clock
The MPC860 accepts the 4 MHz external clock (MODCK[1:2] = 'b11) or 50 MHz external clock (MODCK[1:2] = 'b10), and generates the CLKOUT to clock buffer (U9, CY2305). The CLKOUT frequency is programmable via MPC860 internal clock circuit—4 MHz times 12 (48 MHz), 13 (52 MHz), 50 MHz times 1, or other combinations.
The MPC860 and PCI 9054 are rated at 50 MHz. In turn, the clock buffer generates LCLK to the PCI 9054, POM2_CLK to the POM2 connector, and SDRAM_CLK to the SDRAM. In addition, there is a SPARE_CLK, with a capacitor termination of 10 pF. All clock outputs from U9 (CY2305) should have the same loading to maintain zero delay between input clock (MPC860 CLKOUT) and all outputs.
The phase of the outputs can be adjusted by way of C38, a terminating capacitor on the SPARE_CLK signal. If C38 is larger than the loading of each clock (LCLK, SDRAM_CLK, and POM2_CLK), then the phase shift is negative (that is, output leads input). If C38 is smaller than the loading of each clock, the phase shift is positive (that is, output lags input). Each clock loading should be 10 to 15 pF (plus trace capacitance).
Note: Refer to the section, “Schematics,” for the clock circuits and optional clock termination circuits.
4.4.1 PCI Clock
The PCI Bus Clock (PCLK) supports speeds up to 33 MHz.
4.4.2 Local Clock
The Local Bus Clock (CLKOUT) can be any multiple of 4 MHz, programmable with the MPC860 internal clock generator or 50 MHz with the 50 MHz external oscillator. The PCI 9054RDK-860 is built and set to 50 MHz with an external 50 MHz oscillator.
Note: The PCI 9054 and the MPC860 are limited to 50 MHz.
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
4-3
Section 4 Hardware Architecture
4.5 Memory
The SDRAM and FLASH are connected to the MPC860 memory controller.
4.5.1 Boot ROM (FLASH)
The Boot ROM (FLASH) is described as follows:
• 512 KB (512 kilobits x 8 bits), 90 ns • Access type is Single cycle only • Number of available wait states is six (at 50 MHz, 120 ns FLASH, worst case)
Note: The FLASH contents should be copied to SDRAM after initial boot up. Also, turn on the instruction cache feature to improve performance.
The FLASH contains MPC860 boot code and debug code (PLXMon). The FLASH is accessible by way of the MPC860, as well as the PCI 9054 (Host processor access). The access can be read or write. The MPC860 GPCM is connected to the FLASH with CS0# as the chip select, BS_B0# as the Write Enable signal, and GPL_A1# as the read (OE#) signal. The power supply to U10 (FLASH) can be 3.3 or 5V, selectable by way of R76/R77, depending on the FLASH used. Both the MPC860 and PCI 9054 have a 3.3V supply with 5V-tolerant I/O buffers.
4.5.2 SDRAM
The SDRAM is described as follows:
• 32 MB, 10 ns (100 MHz) • 4 chips x (2 megabits x 8 bits x 4 banks) • Access type is Single cycle or Burst 16 bytes [Four Lword (32-bit) bursts only] • Timing is 5-1-1-1
All SDRAM control signals (UPM(A)—GPL_A[0:3], GPL_A[5], BS_A[0:3], CS1# or CSSDRAM#) originate from the MPC860, with the exception of the CKE signal, which is used to enable or disable the clock signal for power-down purposes. CKE can be enabled or disabled by installing a resistor (R16 or R23, respectively). The CSSDRAM# is connected to the SDRAM chip select [programmable via the MPC860 UPM(A) (user programmable machine A)]. GPL_A0# is connected to the SDRAM AP by way of Mux. GPL_A1# is connected to the SDRAM WE#, GPL_A2# as the SDRAM RAS0#, and GPL_A3# as the SDRAM CAS0#. BS_A[0:3]# are connected to SDRAM DQM[0:3] and act as byte enables.
The GPL_A5# controls the Address Mux unit (U31, U32, and U33). The Mux unit is used to multiplex the row and column address as CAS = A[21:29], RAS = A[9:20]. A[7:8] are used as the bank-select signals.
Note: The SDRAM requires a synchronous clock (SDRAM_CLK) and MA10/AP line to indicate the mode of operation (programming). Refer to the section, “Schematics.”
SDRAM contains the core of standard DRAM, with a clock pin that synchronizes all inputs and outputs (address, data and control signals) to the system clock. These simplify the control interface and eliminate the need to generate asynchronous RAS and CAS strobes, as required by conventional DRAM.
SDRAM incorporates a burst counter used to increment column addresses on each clock for Burst cycles. The burst length and type (sequential or interleaved) is selected by programming an on-chip mode register. The length of the burst sequence may be set by the user and is programmed for one, two, four, eight, or whole page transfers within SDRAM Mode registers.
4-4 PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
Section 4 Hardware Architecture
In addition to the programmable burst length and address-mode selection, CAS Latency and Burst Read/Write mode are programmable. The CAS Latency determines how many clocks are required for data to be valid during Read cycles. The Burst Read/Write Mode bit determines the Burst Read/Write capability of the processor accessing the SDRAM.
Therefore, the mode register should contain 'b100010 for burst of four, Sequential Addressing mode, CAS latency of two, and Burst Read/Write operation. (The MAR data is actually 88h because the address lines are shifted by two Least Significant Bits (LSBs) — SDRAM A[0] is actually LA[2] due to the 32-bit Data Bus.) Refer to SDRAM Data Sheet for more information.
The following data was generated from UPM860.EXE (UPM860.zip file and MPC8XX SDRAM Interface Application Note from the Motorola website).
Note: 100 MHz SDRAM were used to meet the MPC860 timing requirements. The SDRAM is accessible by way of the MPC860 or PCI 9054 (Host processor access).
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
4-5
Section 4 Hardware Architecture
The SDRAM Initialization sequence summary is as follows:
;Load the UPM(A) data
1. Load the UPM(A) data --- see below for the UPM(A) data.
;Memory Bank 1 initialization
2. Init Option_REG_bank1---[OR1]
3. Init BASE_REG_bank1-----[BR1]
;SDRAM_INIT
4. INIT SDRAM mode register --- [MAR] = 0x88.
5. Run MRS command from UPM data 0x2B --- MCR = 0x8000212B
6. Set the UPMA_MODE_REG
7. Set the MCR for refresh --- MCR = 0x80002130 (0x30 of the UPM(A) data has the refresh sequence)
8. Set the UPMA_MODE_REG
UPM_Initialize_Values:
; UPM A RAM Array
; Single Read (Offset 0x0)
.long 0xeffefc04, 0x0ffcfc04, 0xeeefb004, 0x00af3004
.long 0xeffaf000, 0x0ff0f004, 0xfffffc05, 0xfffffc04
; Burst Read (Offset 0x8)
.long 0xeffefc04, 0x0ffcfc04, 0xeeefb004, 0x00af3004
.long 0xf0fff000, 0xf0fff000, 0xe0faf000, 0x0ff0f000
.long 0xfffff005, 0xfffffc04, 0xfffffc04, 0xfffffc04
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
; Single Write (Offset 0x18)
.long 0xeffefc04, 0x0ffcfc04, 0xeeebb000, 0x00a33004
.long 0xeffaf004, 0x0ff0f004, 0xfffffc05, 0xfffffc04
; Burst Write (Offset 0x20)
.long 0xeffefc04, 0x0ffcfc04, 0xeeebb000, 0x00a33000
.long 0xf0fff000, 0xf0fff000, 0xe0faf004, 0x0ff0f004
.long 0xfffffc05, 0xfffffc04, 0xfffffc04, 0xefdafc34
.long 0x0fe0fc34, 0xefaab034, 0x1fb57435, 0xfffffc04
; Refresh (Offset 0x30)
.long 0xeffebc04, 0x0ffc3c04, 0xfffffc04, 0xfffffc04
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc05
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
; Exception (Offset 0x3c)
.long 0xeffffc04, 0x0ffffc04, 0xfffffc05, 0xfffffc04
4-6 PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
Section 4 Hardware Architecture
4.6 Serial Port One of the MPC860 serial ports (SCC1) is used as the RS-232 port. A remote terminal can be connected to this RS-232 port to monitor the PLX ROM program, which is stored in the FLASH.
4.7 Debug Port The PCI 9054RDK-860 supports two MPC860 debug ports — JTAG(J2) and development port (BDM) (J3). The development port supports many different types of Motorola-approved tools, including the FRZ or VFLS[0:1] signals to pins 1 and 6. Refer to the Motorola website for more information.
4.8 Interrupts This section discusses the PCI and Local Bus Interrupt Controller Unit and routing. 4.8.1 MPC860 Critical Interrupt The Local System Error interrupt from the PCI 9054 (RETRY# and TEA#) is routed directly to the Critical Interrupt input on the MPC860 processor. 4.8.2 MPC860 External Interrupt The External Interrupts (RETRY#, IRQ[0:2]3, and IRQ7#) are routed to the MPC860 internal interrupt controller. Interrupts IRQ0#, IRQ2#, and IRQ7# are unused while IRQ1 is connected to the PCI 9054 LINT# pin. LINT# (IRQ1#) can be used to trigger the PCI 9054 DMA Transfer Complete or Doorbell register writes by the Host. The LINT# pin is a bidirectional (input and output) PCI 9054 interrupt pin. 4.8.3 PCI-to-Local interrupt A PCI Master device can generate the local interrupt through the PCI 9054 Doorbell or Mailbox registers. The PCI 9054 interrupt output is connected to the MPC860 IRQ1# pin. The PCI 9054 Local System error (such as a PCI Master abort) can generate TEA# to the MPC860. Refer to the PCI 9054 Data Book for specific interrupts. 4.8.4 PCI Interrupt (INTA#) via the PCI 9054 The bidirectional LINT# pin can be programmed to take the local interrupt source and generate the PCI interrupt (INTA#). INTA# can also be generated from the Local-to-PCI Doorbell register, the DMA Done interrupt, and so forth. Refer to the PCI 9054 Data Book for more information.
4.9 LED Indicators The Green Debug LED is connected to the PCI 9054 USERo pin. Therefore, the Green LED can be turned on or off by writing 1 or 0, respectively, to the PCI 9054 internal register USER bit. The USERo pin can also be used for user-specific applications.
The Red MPC860 Failed LED is connected to the MPC860 FRZ pin. This signal indicates the MPC860 is in Debug Mode or jumped into Debug mode.
4.10 Power Supply
Most of the components are powered from a 3.3V supply. The main PCI power supply can be 5V or 3.3V, selectable by way of R47/R48 configuration.
• If R47 is present and R48 is not, the PCI Bus connector 3.3V power supply is used. In this case, do not install U27, C47, R48, R49, or R50.
• If 3.3V is not available (or if uncertain whether it is “default”), a 5V to 3.3V voltage regulator, such as a U27, can be used (install R48, but not R47).
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
4-7
Section 4 Hardware Architecture
4.11 MPC860 Peripherals Connector (POM2)
The POM2 (PLX Option Module 2) connector contains the necessary signals to utilize all possible MPC860 peripherals, using
• Port A (PA[0:15]) • Port B (PB[14:31]) • Port C (PC[4:15]) • Port D (PD[3:15]) • Input Port B (IP_B[0:7]) • GPL signals • Timer expired (TEXP) • Output Port[0:1]
In addition, there are two groups of power supplies with a configurable 3.3 or 5V supply. Refer to the section, “Serial Interface Pinout,” for peripheral connection pinouts.
+12VCC-12VCC
3.3VCC 5VCC 3.3VCC 5VCC
PB15PB14
PB26PB27
PB29
PB24
PB30
PB25
PB31
PB28
PB18PB19
PB21
PB16
PB22
PB17
PB23
PB20
PC11CTS1#
PC8PC9
PC4PC5
PC13
PC10CD1#
PC15RTS1#
PC7SDACK1#
PC14MDREQ1#
PC6
PC12
VCC_G1
PD10
PD5
PD15
PD3
PD14
PD4
PD8PD7
PD6
PD13
PD9
PD11PD12
IP_B0
IP_B7
IP_B4
IP_B5
IP_B1
IP_B6
IP_B2IP_B3
PA3PA4
PA2
PA11
PA9PA8PA7
PA0 BIGEND#
PA5
PA1 USERIN
PA10
PA6
PA14 TXD1PA13PA12
PA15 RXD1
VCC_G2
R520K0
R510K0
+C6810uF
12
C670.1uF
12
C700.1uF
12
R530K0
R540K0
+C6910uF
12
J7 POM2
303132333435363738394041
50
4243444546474849
29
89
10111213141516171819202122
59
2425262728
567
1234
5152535455565758
60616263646566676869707172737475767778798081828384858687888990919293949596
10099
9798
23
PB14PB15VSSPB16PB17PB18PB19PB20PB21PB22PB23VSS
VSS
PB24PB25PB26PB27PB28PB29PB30PB31
SPARE
VSSPA0PA1PA2PA3PA4PA5PA6VSSPA7PA8PA9PA10PA11VSS
VCC_B
PA12PA13PA14PA15SPARE
GPL_B4#GPL_A5#SPARE
GPL_A4#VSSCLKVSS
PC4PC5PC6PC7PC8PC9
PC10PC11
PC12PC13PC14PC15
PD3PD4PD5PD6
VCC_APD7PD8PD9
PD10PD11PD12PD13PD14PD15IP_B0IP_B1IP_B2IP_B3IP_B4
VCC_BIP_B5IP_B6IP_B7
ALE_BWAIT_B#
TEXPOP1OP0VSS
VCC_AGPL_A0#GPL_A1#
VSS
-12VCC+12VCC
GPL_A2#GPL_A3#
VCC_A
POM2_CLK4
PC[4:15] 2,3,6,9,10
PA[0:15]3,6,10
PB[14:31]3,6,10
PD[3:15] 3,6,10
TEXP 3,6,10
IP_B[7:0] 3,6,10
ALE_B 3,6,10WAIT_B# 3,6,10
OP0 3,6,10OP1 3,6,10
GPL_A4#3,6,9,10
GPL_A0# 3,4,6,9,10GPL_A1# 3,4,6,9,10
GPL_A2# 3,4,6,9,10GPL_A3# 3,4,6,9,10
GPL_B4#3,6,9,10GPL_A5#3,4,6,9,10
Two groups of powersupply to the POM2(PLX Option Module):install correctresistors forrequired power.
*** ***(no_pop)
(no_pop)
Figure 4-1. MPC860 Peripherals Connector (POM2)
4-8 PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
Section 4 Hardware Architecture
4.12 Reset Circuitry
4.12.1 Power-On Reset and Pushbutton Reset
The PCI Bus resets when the RST# signal is active during power-on. The PCI 9054 outputs LRESETo# when RST# is active. All Local devices reset with the LRESETo#.
The on-board Pushbutton resets all Local devices, excluding the PCI 9054. The software must reinitialize the PCI 9054 after all resets.
4.12.2 Register Initialization
The PCI 9054 serial EEPROM contains all critical configuration data for normal PCI Bus operations. These include PnP data, PCI memory resource allocation, and end of the PCI 9054 initializations (such as the Init Done bit). In addition to the serial EEPROM data, the Local processor (MPC860 in this case) can reinitialize the PCI 9054, thereby overwriting the data from the serial EEPROM. Refer to PCI 9054 Data Book and the following serial EEPROM data example for more information.
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
4-9
Section 4 Hardware Architecture
4.12.3 Serial EEPROM Loads
Table 4-2. Long Serial EEPROM Load Registers
Serial EEPROM
Offset
Serial EEPROM
Value (hex) Description Register Bits Affected
0h 1860 Device ID PCIIDR[31:16] 2h 10B5 Vendor ID PCIIDR[15:0] 4h 0680 Class Code PCICCR[23:8] 6h 0001 Class Code, Revision PCICCR[7:0] / PCIREV[7:0] 8h 0000 Maximum Latency, Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] Ah 0100 Interrupt Pin, Interrupt Line Routing PCIIPR[7:0] / PCIILR[7:0] Ch 0000 MSW of Mailbox 0 (User Defined) MBOX0[31:16] Eh 0000 LSW of Mailbox 0 (User Defined) MBOX0[15:0] 10h 0000 MSW of Mailbox 1 (User Defined) MBOX1[31:16] 12h 0000 LSW of Mailbox 1 (User Defined) MBOX1[15:0] 14h FF00 MSW of Range for PCI-to-Local Address Space 0 LAS0RR[31:16] 16h 0000 LSW of Range for PCI-to-Local Address Space 0 LAS0RR[15:0]
18h 0000 MSW of Local Base Address (Re-map) for PCI-to-Local Address Space 0 LAS0BA[31:16]
1Ah 0001 LSW of Local Base Address (Re-map) for PCI-to-Local Address Space 0 LAS0BA[15:0]
1Ch 0100 MSW of Mode/DMA Arbitration Register MARBR[31:16] 1Eh 0000 LSW of Mode/DMA Arbitration Register MARBR[15:0] 20h 0030 MSW of Local Bus Big/Little Endian Descriptor PROT_AREA[15:0] 22h 5524 LSW of Local Bus Big/Little Endian Descriptor LMISC[7:0] / BIGEND[7:0] 24h 0000 MSW of Range for PCI-to-Local Expansion ROM EROMRR[31:16] 26h 0000 LSW of Range for PCI-to-Local Expansion ROM EROMRR[15:0]
28h 0000 MSW of Local Base Address (Re-map) for PCI-to-Local Expansion ROM EROMBA[31:16]
2Ah 0010 LSW of Local Base Address (Re-map) for PCI-to-Local Expansion ROM EROMBA[15:0]
2Ch 4343 MSW of Bus Region Descriptors for PCI-to-Local Accesses LBRD0[31:16]
2Eh 0043 LSW of Bus Region Descriptors for PCI-to-Local Accesses LBRD0[15:0]
30h FF00 MSW of Range for Direct Master-to-PCI DMRR[31:16] 32h 0000 LSW of Range for Direct Master-to-PCI DMRR[15:0]
34h 4000 MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16]
36h 0000 LSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[15:0]
38h 5000 MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16]
3Ah 0000 LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[15:0]
3Ch 0000 MSW of PCI Base Address (Remap) for Direct Master-to-PCI DMPBAM[31:16]
3Eh 0003 LSW of PCI Base Address (Remap) for Direct Master-to-PCI DMPBAM[15:0]
40h 0000 MSW of PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration DMCFGA[31:16]
42h 0000 LSW of PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration DMCFGA[15:0]
4-10 PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
Section 4 Hardware Architecture
Table 4-3. Extra Long Serial EEPROM Load Registers
Serial EEPROM
Offset
Serial EEPROM
Value Description Register Bits Affected
44h 9054 Subsystem ID PCISID[15:0] 46h 10B5 Subsystem Vendor ID PCISVID[15:0] 48h FF00 MSW of Range for PCI-to-Local Address Space 1
(1 MB) LAS1RR[31:16]
4Ah 0000 LSW of Range for PCI-to-Local Address Space 1 (1 MB)
LAS1RR[15:0]
4Ch 0000 MSW of Local Base Address (Remap) for PCI-to-Local Address Space 1
LAS1BA[31:16]
4Eh 0001 LSW of Local Base Address (Remap) for PCI-to-Local Address Space 1
LAS1BA[15:0]
50h 0000 MSW of Bus Region Descriptors (Space 1) for PCI-to-Local Accesses
LBRD1[31:16]
52h 0043 LSW of Bus Region Descriptors (Space 1) for PCI-to-Local Accesses
LBRD1[15:0]
54h 0000 MSW of Hot Swap Control register Reserved 56h 4C06 LSW of Hot Swap Control register HS_NEXT[7:0] / HS_CNTL[7:0]
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
4-11
Section 4 Hardware Architecture
4.13 Arbitration
PCI Bus arbitration is performed using the PCI Host arbiter when the PCI 9054 needs the PCI Bus, while the Local Bus uses the built-in MPC860 arbiter when the PCI 9054 needs the Local Bus. The PCI Bus arbitration signals are REQ# and GNT#. The Local Bus arbitration signals are BR#, BG#, and BB#.
4.14 Power Management
Power Management uses the PME# pin (four stages) (refer to PCI 9054 Data Book). The PCI 9054 does not retain Power Shutdown mode; however, the LCLK (local clock) can be slowed or shut down from the external clock circuit to conserve power. PME# and internal registers for Power Management are used by the Local and Host processors to control board power management. If the clock is removed (0 Hz), the PCI 9054 contains all the configuration data as long as the power is supplied and the clock returns with a smooth transition. If power is removed, the software must reconfigure the PCI 9054.
4.15 Prototype Area
The PCI 9054RDK-860 provides a prototype area that allows users to incorporate custom-designed circuitry. This area contains common surface-mount footprints, including two 44-pin TQFPs, two 20-pin SOs, two 16-pin SOs, a 20-pin PLCC, a 44-pin PLCC, and a 68-pin PLCC.
In addition, a standard 0.100-inch through-hole array is included, as well as connections for +3.3V and ground.
4.16 Test Connectors
All Local Address and Data lines can be monitored by way of J8, and all Local Bus Control signals can be monitored by way of J9.
4.17 Test Points
All schematic signals have test points, which are coincident to board “VIAs.” The PCI 9054RDK-860 is an example of how to implement a circuit board for an Automated Test Unit (ATU) fixture. Refer to the GERBER files on the RDK CD-ROM for details.
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved. 4-12
Section 4 Hardware Architecture
4.18 Jumpers and Connectors Summary
4.18.1 Configuration Jumpers (Resistors)
The following table describes configuration jumpers (resistors).
Table 4-4. Configuration Jumpers (Resistors)
Resistor Description
R60 and R62, or R61 and R63 Configures the type of Development Port tool used (default). Install R61 and R63 to use the tools requiring VFLS[0:1].
R76/R77 Selects the FLASH power source. Install R76 if FLASH operates with 3.3V (default). Install R77 if FLASH operates with 5V.
R16/R25 Enable/disable the SDRAM clock input. Enables it when R16 is installed (default).
R38/R39
MODCK1 state during power-on. If R38 is installed, MODCK1 = 1. R40/R41 — MODCK2 state during power-on. If R40 is installed, MODCK0 = 1. Install R38 and R40 if 4 MHz OSC is used. (Default) Install R38 and R41 if 50 MHz OSC is used.
R42/R43 D[5] state during power-on. If R42 is installed, D[5] = 1, boot port size is 8-bit (default).
R70/R71 D[7] state during power-on. If R70 is installed, D[7] = 1, initial internal register base address = 0xFF00_0000 (default).
R72/R73, R74/R75 D[9:10] state during power-on. If R72 and R74 are installed, D[9:10] = 11, debug pin configuration (default).
R64/R65, R66/R67 D[11:12] state during power-on. If R64 and R66 are installed, D[11:12] = 11, external bus division factor (default).
R48/R47
Power Source: 1. If R48 is installed, the 3.3V power is regulated from PCI 5V. 2. If R47 is installed, the board uses the PCI Bus 3.3V.
(Do not install U27 and R48.)
R51/R52 and R53/R54—POM2
Power source. Refer to the section, ”Schematics, sheet 8.” 1. Default. Install R51 and R54 for POM2 connector 3.3V/5VCC supply.
(Do not install R52 and R53.) 2. Connect desired power supply combinations.
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
4-13
Section 4 Hardware Architecture
4.18.2 Jumpers, Test Points, and Connectors
The following table describes jumpers, test points, and connectors.
Table 4-5. Jumpers, Test Points, and Connectors
Jumper Description
J1
PCI 9054 mode and test configuration. 1. Pins 1 and 2 are open (default)—TEST = 0; test function is disabled for normal operation. 2. Pins 3 and 4 are open (default)—MODE1 = 1, and pins 5 and 6 are open (default)—MODE0 = 1.
MODE[1:0] are used to program the PCI 9054 Local Bus mode. When these bits have a value of 11, the PCI 9054 operates in M mode (MPC860 mode).
Refer to PCI 9054 Data Book for more information.
J2 MPC860 JTAG connector.
J3 MPC860 Development Port connector.
J6 PCI edge connector.
J7 POM2 (PLX Option Module 2).
J8 Local Address and Data test points.
J9 Local Bus Control Signal test points.
4.19 Special Considerations
Note the following when using the PCI 9054RDK-860:
• BDIP# is generated only if the BTERM bit is reset (0). Therefore, if more than four Lwords are needed, use the BURST# signal (instead of BDIP#) to terminate the Burst sequence. To burst more than four Lwords, use of synchronous devices is recommended. Refer to CompactPCI 9054RDK-860 Hardware Reference Manual for more information on how to use synchronous-burst SRAM.
• The BB# line requires a 3.9K pull-up resistor. • The EEDI/EEDO pin requires a 1K-ohm pull-down resistor if the serial EEPROM is not
present and the MPC860 does not initialize the PCI9054. The 1K-ohm pull-down resistor forces data input to the PCI 9054 to be 0, which is required to bypass the serial EEPROM load. Because the EEDI/EEDO pin is bidirectional, 1K is required to quickly pull down the line because the PCI 9054 is driven high during the last clock.
• The EEDI/EEDO pin requires a 3.9K-ohm pull-up resistor if serial EEPROM is present.
4-14 PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
5. Software Architecture
5.1 PCI SDK
A complete PCI 9054 API library is available from PLX Technology (refer to the section, “Customer Support,” for information on how to contact PLX).
5.1.1 PLXMon (Uses PCI SDK)
PLXMon is used on the Host Bus (PC). PLXMon runs from FLASH memory on the Local Bus.
5.1.2 Windows Device Drivers
Drivers that use the API library are available from PLX Technology (refer to the section, “Customer Support,” for information on how to contact PLX).
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
5-1
6. Serial Interface Pinout
6.1 SCC1
Table 6-1. UART
MPC860 Pin # POM2 Signal Name Signal Name Description
D17 PA[14] TXD1 Transmit data output for SCC1
C18 PA[15] RXD1 Receive data input for SCC1
N19 PB[19] RTS1# Request to send modem line for SCC1
J19 PC[11] CTS1# Clear to send modem line for SCC1
K19 PC[10] CD1# Carrier detect modem line for SCC1
Table 6-2. HDLC Controller
MPC860 Pin # POM2 Signal Name Signal Name Description
D17 PA[14] TXD1 Transmit data output for SCC1
C18 PA[15] RXD1 Receive data input for SCC1
M19 PA[7] CLK1 Clock for SCC
N19 PB[19] RTS1# Request to send modem line for SCC1
J19 PC[11] CTS1# Clear to send modem line for SCC1
K19 PC[10] CD1# Carrier detect modem line for SCC1
Table 6-3. Transparent Controller
MPC860 Pin # POM2 Signal Name Signal Name Description
D17 PA[14] TXD1 Transmit data output for SCC1
C18 PA[15] RXD1 Receive data input for SCC1
M19 PA[7] CLK1 Clock for SCC
N19 PB[19] RTS1# Request to send modem line for SCC1
J19 PC[11] CTS1# Clear to send modem line for SCC1
K19 PC[10] CD1# Carrier detect modem line for SCC1
U18 PB[14] RSTRT1# Serial CAM Interface output signals that marks start of a frame
E19 PB[27] BRG01 BRG1 output clock
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
6-1
Section 6 Serial Interface Pinout
Table 6-4. Ethernet Controller
MPC860 Pin # POM2 Signal Name Signal Name Description
D17 PA[14] TXD1 Transmit data output for SCC1
C18 PA[15] RXD1 Receive data input for SCC1
M19 PA[7] CLK1, RCLK Clock for SCC
N19 PB[19] RTS1#, TENA Request to send modem line for SCC1
J19 PC[11] CTS1#, CLSN Clear to send modem line for SCC1
K19 PC[10] CD1#, RENA Carrier detect modem line for SCC1
U18 PB[14] RSTRT1# Serial CAM Interface output signals that marks start of a frame
L19, K17 PB[22],PB[23]
SDACK2-1 SDMA acknowledge 2-1 (Ethernet CAM
interface signal)
K3, J1, J2, H1
IP_B[6], ALE_B, IP_B[2], IP_B[7] AT0-AT3 Address type 0-3; 1 = CPM transaction
initiator, 0 = CPU transaction initiator
C17 PB[31] REJECT1 SCC1 CAM interface reject pin
Table 6-5. I2C
MPC860 Pin # POM2 Signal Name Signal Name Description
E19 PB[27] I2C SDA I2C serial data pin
F19 PB[26] I2C SCL I2C serial clock pin
M17 PA[6] BRGLCK1 BRGs external clock inputs
Table 6-6. Centronic Transmitter
MPC860 Pin # POM2 Signal Name Signal Name Description
U18, R17, N16, P18, N17, N19, L16, K16, L19, K17, J18, J16, F19, E19, D19, E16, C19, C17
PB[14:31] PB[14:31] General Purpose I/O Port B bits [14:31]
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved. 6-2
Section 6 Serial Interface Pinout
6.2 SCC2
Table 6-7. UART
MPC860 Pin # POM2 Signal Name Signal Name Description
K16 PB[21] TXD2 Transmit data output for SCC2
L16 PB[20] RXD2 Receive data input for SCC2
D18 PC[14] RTS2# Request to send modem line for SCC2
L18 PC[9] CTS2# Clear to send modem line for SCC2
M18 PC[8] CD2# Carrier detect modem line for SCC2
Table 6-8. HDLC
MPC860 Pin # POM2 Signal Name Signal Name Description
K16 PB[21] TXD2 Transmit data output for SCC2
L16 PB[20] RXD2 Receive data input for SCC2
D18 PC[14] RTS2# Request to send modem line for SCC2
L18 PC[9] CTS2# Clear to send modem line for SCC2
M18 PC[8] CD2# Carrier detect modem line for SCC2
M17 PA[6] CLK2 Input clock for SCC
Table 6-9. Transparent Controller
MPC860 Pin # POM2 Signal Name Signal Name Description
K16 PB[21] TXD2 Transmit data output for SCC2
L16 PB[20] RXD2 Receive data input for SCC2
D18 PC[14] RTS2# Request to send modem line for SCC2
L18 PC[9] CTS2# Clear to send modem line for SCC2
M18 PC[8] CD2# Carrier detect modem line for SCC2
M17 PA[6] CLK2 Input clock for SCC
F19 PB[26] BRG02 BRG2 output clock
Note: No RSTRT# support.
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
6-3
Section 6 Serial Interface Pinout
6.3 SCC3
Table 6-10. UART
MPC860 Pin # POM2 Signal Name Signal Name Description
W18 PD[10] TXD3 Transmit data output for SCC3
T16 PC[11] RXD3 Receive data input for SCC3
T15 PD[7] RTS3# Request to send modem line for SCC3
M16 PC[7] CTS3# Clear to send modem line for SCC3
R19 PC[6] CD3# Carrier detect modem line for SCC3
Table 6-11. HDLC
MPC860 Pin # POM2 Signal Name Signal Name Description
W18 PD[10] TXD3 Transmit data output for SCC3
T16 PC[11] RXD3 Receive data input for SCC3
T15 PD[7] RTS3# Request to send modem line for SCC3
M16 PC[7] CTS3# Clear to send modem line for SCC3
R19 PC[6] CD3# Carrier detect modem line for SCC3
M18 PC[8] CLK3 Clock for SCC
Table 6-12. Transparent Controller
MPC860 Pin # POM2 Signal Name Signal Name Description
W18 PD[10] TXD3 Transmit data output for SCC3
T16 PC[11] RXD3 Receive data input for SCC3
T15 PD[7] RTS3# Request to send modem line for SCC3
M16 PC[7] CTS3# Clear to send modem line for SCC3
R19 PC[6] CD3# Carrier detect modem line for SCC3
M18 PC[8] CLK3 Clock for SCC
R17 PB[15] BRGOUT3 Output clock for BRG3
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved. 6-4
Section 6 Serial Interface Pinout
6.4 SCC4
Table 6-13. UART
MPC860 Pin # POM2 Signal Name Signal Name Description
W17 PD[8] TXD4 Transmit data output for SCC4
V17 PD[9] RXD4 Receive data input for SCC4
V16 PD[6] RTS4# Request to send modem line for SCC4
T18 PC[5] CTS4# Clear to send modem line for SCC4
T17 PC[4] CD4# Carrier detect modem line for SCC4
Table 6-14. HDLC
MPC860 Pin # POM2 Signal Name Signal Name Description
W17 PD[8] TXD4 Transmit data output for SCC4
V17 PD[9] RXD4 Receive data input for SCC4
V16 PD[6] RTS4# Request to send modem line for SCC4
T18 PC[5] CTS4# Clear to send modem line for SCC4
T17 PC[4] CD4# Carrier detect modem line for SCC4
P19 PA[4] CLK4 Clock for SCC
Table 6-15. Transparent Controller
MPC860 Pin # POM2 Signal Name Signal Name Description
W17 PD[8] TXD4 Transmit data output for SCC4
V17 PD[9] RXD4 Receive data input for SCC4
V16 PD[6] RTS4# Request to send modem line for SCC4
T18 PC[5] CTS4# Clear to send modem line for SCC4
T17 PC[4] CD4# Carrier detect modem line for SCC4
D19 PB[28] BRGO4 BRG4 output clock
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
6-5
Section 6 Serial Interface Pinout
6.5 MISC
Table 6-16. SI with TDM (Time Slot Assignor)
MPC860 Pin # POM2 Signal Name Signal Name Description
T17 PC[4] L1RSYNCA Receive sync input for serial interface TDM Port A
U17 PD[15] L1TSYNCA Input transmit data sync to TDM Channel A
R16 PD[12] L1RSYNCB Receive sync input for serial interface TDM Port B
V18 PD[13] L1TSYNCB Input transmit data sync to TDM Channel B
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved. 6-6
7. Customer Support Prior to contacting PLX Customer Support, please be situated close to the computer in which the RDK board is installed and be prepared to provide the following information:
• Evaluation board serial number • PLX PCI RDK board model number • PLX PCI SDK version • Operating System version and type • Description of intended design:
• PLX PCI chip • Processor • Local Operating System and version (if any) • I/O
• Description of problem and steps to recreate the problem (if reporting a problem)
You may contact PLX Customer Support at:
Address PLX Technology, Inc.
Attn: Customer Support 870 Maude Ave Sunnyvale, CA 94085
Phone 408-774-9060 800-759-3735 Fax 408-774-2169 Website http://www.plxtech.com
For technical support on the Web, go to http://www.plxtech.com/support/.
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
7-1
8. References
1. PLX Technology, Inc., PCI 9054 Data Book, http://www.plxtech.com
2. Motorola, MPC860 Data Book
3. PCI SIG, PCI Specification Rev. 2.1 and 2.2
4. Motorola, SDRAM Data Sheet
5. I2O Special Interest Group, Intelligent I/O (I2O) Architecture Specification Revision 1.5
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
8-1
9. Bill of Materials & Schematics PLX Part #: 91-0002-300-A
Table 9-1. BOM – Components Should be Assembled Item# Qty Manufacture Manufacture Part
Number Description Package Type Source Part Reference
3 43 Kemet C0805C104M5UAC 0.1uF, 50V 20% Capacitor
SMT, 0805 Electrosonic C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C13 C14 C15 C16 C18 C19 C20 C21 C22 C23 C24 C25 C26 C34 C45 C48 C54 C55 C56 C57 C58 C59 C61 C63 C65 C67 C70 C71 C73 C75 C77 C81
4 11 Panasonic ECS-T1DC106R 10uF, 20V Tantalum Capacitor
SMT, C Case Newark C12 C46 C47 C49 C50 C51 C52 C53 C68 C69 C79
5 1 Panasonic ECJ-2VC1H151J 150pF, 50V 5% Capacitor
SMT, 0805 Electrosonic C17
6 9 Kemet C0805C103M5UAC 0.01uF, 50V 20% Capacitor
SMT, 0805 Electrosonic C27 C60 C62 C64 C66 C72 C74 C76 C78
7 1 Panasonic ECU-V1H100JCN 10pF, 50V 5% Capacitor SMT, 0805 Digikey C28
9 4 Kemet T491A104K035AS 0.1uF, 35V Tantalum Capacitor
SMT, A Case Electrosonic C80 C82 C83 C84
10 1 Agilent Tech. HSMG-C650 GREEN_LED SMT Newark D1
11 1 Agilent Tech. HSMS-C650 RED_LED SMT Newark D2
18 1 Molex 15-91-1062 6-Pin header, 3x2 Dual-Row .1",unshrouded header
SMT FAI J1
20 1 Molex 15-91-1102 10-Pin header, 5x2 Dual-Row .1", unshrouded header
SMT FAI J3
21 1 N/A N/A 32-bit PCI, Universal Card Edge Connector
N/A J6
22 1 AMP 1-104652-0 100-Pin Female Squall Connector, 50x2 Dual row
SMT Digikey J7
23 2 Molex 15-91-1722 72-Pin header, 36x2 Dual row .1", Unshrouded Header
SMT FAI J8 J9
29 43 CTS 742C-08-3-103J 10K Ohm Isolated resistor network
SMT, 0603X4 Digikey RN1 RN2 RN3 RN4 RN5 RN6 RN7 RN8 RN9 RN10 RN11 RN12 RN17 RN18 RN19 RN20 RN21 RN22 RN23 RN24 RN25 RN26 RN27 RN28 RN29 RN30 RN31 RN32 RN33 RN34 RN35 RN36 RN37 RN38 RN39 RN40 RN41 RN42 RN43 RN44 RN45 RN46 RN47
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
9-1
Section 9 Bill of Materials & Schematics
Item# Qty Manufacture Manufacture Part Number
Description Package Type Source Part Reference
30 24 Philips RC11J10K0 10K Ohm, 1/10W, 5% Resistor
SMT, 0805 Electrosonic R1 R2 R3 R4 R6 R9 R11 R12 R13 R36 R37 R38 R42 R45 R55 R56 R57 R58 R59 R64 R66 R70 R72 R74
31 7 Philips RC11J1K00 1K Ohm, 1/10W, 5% Resistor
SMT, 0805 Electrosonic R7 R8 R10 R41 R79 R81 R82
32 10 Philips RC11J22R1 22 Ohm, 1/10W, 5% Resistor
SMT, 0805 Electrosonic R14 R15 R17 R18 R19 R21 R22 R24 R68 R69
33 7 Vishay WSL1206R010FRE4 0 Ohm, 1/4W, 1% Resistor
SMT, 1206 Newark R16 R48 R51 R54 R61 R63 R76
34 5 Philips RC11J33R 33 Ohm, 1/10W, 5% Resistor
SMT, 0805 Electrosonic R20 R23 R26 R27 R28
36 3 Philips RC11J110R 110 Ohm, 1/10W, 5% Resistor
SMT, 0805 Electrosonic R44 R46 R49
37 1 Philips RC11J180R 180 Ohm, 1/10W, 5% Resistor
SMT, 0805 Electrosonic R50
38 2 Panasonic ERJ-6GEYJ392V 3.9K Ohm, 1/10W, 5% Resistor
SMT, 0805 Digikey R80 R83
40 1 Omron B3S-1002 Tactile Pushbutton Switch
SMT, 4 Pin, 4.2x9.0mmm
Digikey SW1
43 1 PLX PCI 9054-AC50PI PLX PCI9054 Bridge Chip
PQFP-176 Pin PLX U1
45 1 Motorola XPC860MHZP50C1 Motorola MPC860 50Mhz
BGA-357 Pin FAI U3
46 1 MTRON M213TAN50.00 50.00 Mhz Osc, 3.3V SMT, 4 pin lead FAI U4
47 4 Samsung K4S640832D-TC10 2MegX8X4banks 10ns SDRAM
TSOP-54 Pin U5 U6 U7 U8
48 1 Cypress CY2305SC-1 3.3V Zero delay buffer SOIC-8 Pin Cypress U9
49 1 Augat PCS-032SMU-11 32 Pin PLCC socket PLCC-32 Pin Electrosonic U10
50 1 Maxim MAX6306UK30D1-T 3.3V Programmable reset device
SOT23-5 Newark U20
51 3 Fairchild NC7SZD384P5 1-bit Bus switch SC70-5 Digikey U24 U25 U26
52 1 Linear Tech. LT1587CM 3A Adjustable Voltage Regulator
3 Pin Lead DD PAK
Electrosonic U27
53 1 Maxim MAX3245CAI RS-232 Transceiver SSOP-28 Pin Digikey U28
54 3 Fairchild 74LCX257MTC Quad 2-input Multiplexer TSSOP-16 Pin Digikey U31 U32 U 33
55 1 Fairchild 74LCX245MTC Bus Transceiver TSSOP-20 Pin Digikey U34
56 1 PLX 90-0002-300-A PCB, PCI9054RDK-860(Use schematic
91-0002-300-A Rev 300)
9-2 PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
Section 9 Bill of Materials & Schematics
Table 9-2. BOM – Through Hole Components Item# Qty Manufacture Manufacture Part
Number Description Package Type Source Part Reference
19 1 Leoco 2556P06TA00 6-Pin header, 6x1 Single-Row .1", unshrouded header
Thru hole Prolex J2
24 1 Toko 262LY-822K 30mA Inductor, 8RBS Low Profile
Thru hole Digikey L1
26 1 SPC DE-9P-FRS DE-9 Male PCB mount RS232 connector
Thru hole Newark P1
44 1 SPC MPSL-08T 8 Pin DIP Socket, 300 mil
Thru hole Newark U2
Table 9-3. BOM – Manually Inserted Components Item# Qty Manufacture Manufacture Part
Number Description Package Type Source Part Reference
27 1 Microchip 93LC56B 2K Serial EEPROM DIP-8 Pin Newark P2
28 1 Atmel AT29LV040-12JC 512K X 8, 120ns, 3.3V Flash Memory
PLCC-32 Pin Newark P3
Table 9-4. BOM – Miscellaneous Components Item# Qty Manufacture Manufacture Part
Number Description Package Type Source Part Reference
1 1 Velostat 2100R/7X15 7" X 15" Antistatic Bag N/A FAI BAG1
2 1 Serial cable, 25 pin Female to 9 pin Female (null modem)
N/A CABLE1
25 1 PCI 9054RDK-860 PCB Bracket
N/A DTI Panel1
39 2 Philips 501-002 Panel screws N/A Spaenaur SCREW1, SCREW2
Table 9-5. BOM – Components Should Not Be Assembled Item# Qty Manufacture Manufacture Part
Number Description Package Type Source Part Reference
8 5 Panasonic ECU-V1H220JCN 22pF, 50V 5% Capacitor SMT, 0805 Digikey C29 C30 C31 C32 C33
30 1 Philips C11J10K0 10K Ohm, 1/10W, 5% Resistor
SMT, 0805 Electrosonic R40
31 9 Philips RC11J1K00 1K Ohm, 1/10W, 5% Resistor
SMT, 0805 Electrosonic R5 R39 R43 R65 R67 R71 R73 R75 R78
33 7 Vishay WSL1206R010FRE4 0 Ohm, 1/4W, 1% Resistor
SMT, 1206 Newark R25 R47 R52 R53 R60 R62 R77
35 5 Philips RC11J51R 51 Ohm, 1/10W, 5% Resistor
SMT, 0805 Electrosonic R29 R30 R31 R32 R33
PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
9-3
Section 9 Bill of Materials & Schematics
The following are the PCI 9054RDK-860 circuit board schematics.
Note: “Page 5 of 11” of the schematics is intentionally omitted.
9-4 PCI 9054RDK-860 Hardware Reference Manual v2.3 © 2005 PLX Technology, Inc. All rights reserved.
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
PCI9054RDK-860 BLOCK DIAGRAM
ECN HISTORY
ECN NUMBER DATE NOTE
xxx-xxx 04/30/98 1. BDM signals added: R60, R61, R62, and R63 to include VFLS[1:0] and FRZto the BDM connector.2. Added pull up to D11 and D12: R64, R65, R66, R67, U29, and U30.
06/22/98xxx-xxx 1. SDRAM: added ADDR MUX(U31,U32,U33): Changed MA[0:11] to SDRAM, Added R68 andR69 for A7 and A8. Changed WE#(GPL_A1#).2. FLASH: Added 3.3V or 5V(VCC) PS Option. Changed WE#(BS_B0#).3. SRAM: added BDIP# signal to the glue.4. Power UP config: added D7,D9,D10 (U34,U35,U36) for the power up configurations.5. Changed the PU/PD (R)s for the Power Up Configurations.6. Added PU/PD (R)s for the MPC860 JTAG Port.
Added R78 & R79 (Wait control input to UPM)07/02/98xxx-xxx
xxx-xxx 08/08/98 1. Removed SRAM: Lattice and SRAMs.2. Changed R5 to 1K (EEDI/O pull down R).3. Added Pull-Up Resistor(510 ohm) for BB#.4. Added Pull-Down Resistor for TCK and TRST#(1K ohm).5. Fixed SDRAM address MUX unit.
PCI9054 PG 2
LOCAL BUS
PCI BUS
NOTE: (otherwise specified)1. All resistors are EIA case style 0805, 5% tolerance.2. All .1uF caps are EIA case style 0805, 10% tolerance.3. All 0K0 resistors are 1210 type and less than 0.01 ohms
SDRAM (32MB) PG 4
MPC860 PG 3
MPC860 Peripherals PG 8
FLASH (512KB) PG 4
SERIAL PORT PG 8
xxx-xxx 08/21/98 1. TSIZ0 (pin 92) and TSIZ1 (pin 91) were swapped.
(*** indicates default, do not install other)
xxx-xxx 6/25/02 Correct pull-up resistor at U1-166. It was R81, now is R831.2. Update BOM to reflect PCB board Rev 90-0002-300-A, and Document Number
91-0002-300-A 300
BLOCK DIAGRAM
PLX TECHNOLOGY870 Maude Ave, Sunnyvale, CA 94085
Custom
1 11Friday, July 12, 2002
WWW.PLXTECH.COMTitle
Size Document Number Rev
Date: Sheet of
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
TO PCI9054 POWER PINS
MODE: [MODE1:MODE0] = 11; M-MODE
(no_pop)
EEPROM present : install R83, not install R5
EEPROM not present : install R5, not install R83
Normal operation:J1:1-2 openJ1:3-4 openJ1:6-5 open
91-0002-300-A 300
PCI 9054
PLX TECHNOLOGY870 Maude Ave, Sunnyvale, CA 94085
Custom
2 11Friday, July 12, 2002
WWW.PLXTECH.COMTitle
Size Document Number Rev
Date: Sheet of
A28
A26
A7
A0
A6
A20
A15A14
A29
A23
A16A17
A8A9
A24
A12
A1
A19
A10
A27
A21
A11
A2
A18
A25
A3
A13
A5
A22
A4
D28
D30
D10
D16
D22
D26
D8
D2
D6
D20
D0
D19
D29
D9
D13
D11
D23
D17
D15
D27
D21
D31
D3
D7
D25
D1
D5
D14
D4
D24
D12
D18
PU213PU217
AD15
AD27
AD17
AD3
AD6
AD10
AD30
AD12
AD22
AD25
AD18
AD26
AD8
AD16
AD21
AD28
AD31
AD20AD19
AD0
AD2
AD23
AD29
AD11
AD7
AD4AD5
AD9
AD13
AD1
AD24
AD14
PU201
ENUM#
PU206
PU208PU209
MDREQ1#
PU207
PU214
PU205PU204
PU202
PU216
PU212
A31A30
EESKEECS
LEDon/LEDin
PU211PU210
EEDIEEDO
MODE1MODE0
A0
A2A1
A3
A5A4
A7A6
A8
A10A9
A11
A15A14A13A12
A22A23
A20A21
A19
A17A18
A16
A31
A29A30
A28
A26
A24A25
A27
PU202PU204
PU201
PU205
PU206
PU209
PU207PU208
PU214
PU217PU216
PU210
PU212PU211
PU213
BB#
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
R6 10K
R8 1K
R10 1K
R7 1K
R9 10K
R11 10K
R1 10K
R2 10K
R51K
R310K
J1
2X3 PIN HEADER
1 23 45 6
RN1
742-08-3-103-J-XX
1234 5
678
RN3
742-08-3-103-J-XX
1234 5
678
RN7
742-08-3-103-J-XX
1234 5
678
RN2
742-08-3-103-J-XX
1234 5
678
RN4
742-08-3-103-J-XX
1234 5
678
RN6
742-08-3-103-J-XX
1234 5
678
RN8
742-08-3-103-J-XX
1234 5
678
RN5
742-08-3-103-J-XX
1234 5
678
RN9
742-08-3-103-J-XX
1234 5
678
RN10
742-08-3-103-J-XX
1234 5
678
RN11
742-08-3-103-J-XX
1234 5
678
RN12
742-08-3-103-J-XX
1234 5
678
U2
93LC56B (8DIP-Socket)
1234
8765
CSSKDIDO
VCCPRE
PEGND
R410K
R80 3.9KR83
3.9K
PCI Signals
PCI Signals
PCI Signals
PCI Signals
PCI Signals
U1 PCI 9054 (PQFP)
150134
135
163
148
153
158
149
139
145
90
164
138
170
151
137
165
136
144
166
169
7171
155
142157
160
156
152
1439493
9291
146159
52167
10
154
62
53
173174175234
14153132333436373839404243464748495051
5
3528 89
115
9945 70
19
109
116
27
133
16814
114
7
61
111213
9
29
6944
8
8824
6
108
17
16
132
21
140
18
172
161
30
176
23
41
22
6425
54
26
55565758
117
596063
125
65666768
124
71727374
123
75767778
122
798081
121
82838485
120
8687
119118
114
112
131
111
130
110
129128
107
127126
106105104103102101
113
10098979695
162
1 20
BB#/BREQiBI#/BTERM#
TA#/READY#
BIGEND#/WAIT#
BURST#/BLAST#
MDREQ#/DMPAF/EOT#
USERo/DREQ0#/LLOCKo#
RETRY#/BREQo
DP0
TS#/ADS#
RD/WR#
EECS
DP1
PCLK
BDIP#/WAITi#
DP2
EESK
DP3
BG#/LHOLDA
EEDI/DO
RST#
IDSELGNT#
TEST
LCLKMODE1
CCS#
MODE0
LRESETo#
BR#/LHOLDLA0/LBE0#LA1/LBE1#
TSIZ0/LBE2#TSIZ1/LBE3#
TEA#/LSERR#USERi/DACK0#/LLOCKi#
ENUM#PME#
AD22
LINTi#/LINTo#
VD
D
LEDon/LEDin
AD31AD30AD29AD28AD27AD26
AD18AD17AD16AD15AD14AD13AD12AD11AD10
AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0
AD25
VD
DV
DD
VD
D
VS
S
VD
D
VD
D
VD
D
VS
S
VD
DV
DD
VS
S
VD
DINTA#
VD
DV
DD
VS
S
AD21AD20AD19
AD23
PAR
VS
S
VS
S
AD24
VS
SLOCK#
C/BE3#
VS
S
FRAME#
C/BE2#
VS
S
TRDY#
VS
S
IRDY#
REQ#
VS
S
C/BE1#
VS
S
STOP#
C/BE0#
DEVSEL#
LA23PERR#
LA31
SERR#
LA30LA29LA28LA27
LAD14
LA26LA25LA24
LAD6
LA22LA21LA20LA19
LAD7
LA18LA17LA16LA15
LAD8
LA14LA13LA12LA11
LAD9
LA10LA9LA8
LAD10
LA7LA6LA5LA4
LAD11
LA3LA2
LAD12LAD13
LAD15
LAD17
LAD0
LAD18
LAD1
LAD19
LAD2LAD3
LAD20
LAD4LAD5
LAD21LAD22LAD23LAD24LAD25LAD26
LAD16
LAD27LAD28LAD29LAD30LAD31
VD
D
VD
DV
DD
C1 0.1uF
12
C5 0.1uF
12
C4 0.1uF
12
C3 0.1uF
12
C2 0.1uF
12
C6 0.1uF
12
C10 0.1uF
12
C9 0.1uF
12
C8 0.1uF
12
C7 0.1uF
12
C11 0.1uF
12
D[0:31]3,4,6,9,10
CLK7,10
BR# 3,9,10
A[0:31]3,4,9,10
RST#7,10GNT#7,10
IDSEL7,10
TEST9,10
LCLK4,9,10
CS9054#3,9,10BG#3,9,10
AD[31:0] 7,10
C/BE0# 7,10C/BE1# 7,10C/BE2# 7,10C/BE3# 7,10
DEVSEL# 7,10
LOCK# 7,10PAR# 7,10REQ# 7,10INTA# 7,10PME# 7,10
TS# 3,9,10BURST# 3,9,10RD/WR# 3,9,10TA# 3,9,10
LINT# 3,9,10
BI# 3,9,10
TEA# 3,9,10
BDIP# 3,9,10
DP0 3,9,10DP1 3,9,10DP2 3,9,10DP3 3,9,10
BB# 3,9,10RETRY# 3,9,10
LRESETO# 8,10LLOCKI# 9,10
PC14 3,6,8,9,10
USERO 6,9,10BIGEND# 9,10
EEDO 10EESK 10EECS 10
TSIZ03,9,10TSIZ13,9,10
FRAME# 7,10
STOP# 7,10TRDY# 7,10IRDY# 7,10
SERR# 7,10PERR# 7,10
MODE010MODE110
LEDon/LEDin 10ENUM# 10
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
JTAG Port
SEE PG8 FOR BYPASS CAPS
Development Port(no_pop)
(no_pop)
***
***
91-0002-300-A 300
MPC860
PLX TECHNOLOGY870 Maude Ave, Sunnyvale, CA 94085
Custom
3 11Friday, July 12, 2002
WWW.PLXTECH.COMTitle
Size Document Number Rev
Date: Sheet of
D26
PB23
PB25
IP_B1
PC12
BADDR30
PB18
PB29
IP_B6 DSDI
PD3
PD10PD11
A25
A10
A7
D14
PA5
PA13
PB15
IP_B4
PD15
A8
DSDO
PC5
BADDR28
D9
PA9
PB16
PB24
PD7
PD12
A28
A2
BADDR29
D22
PA14 TXD1
IP_A6
D10
D13
D18
PA8
PB20
PB26
PD8PD9
A9
IP_A7
PC6
D0
D15
PA10
PB19
PB28
PD6
PD14
A22
A17
A12
PC4
DSCK
A24
A16
TDI
IP_A3
D12
D16
D17
D24
PA3PA4
PA11
PB21
PB30
PD5
A30
A18
A5
A0
PC14 MDREQ1#PC15 RTS1#
D20
PD13
A29
A26
A21A20
A4A3
TRST#TDO
IP_A5
PC11 CTS1#
D3
D19
PA0
PA7
PA12
PA15 RXD1
PB22
A19
TMSTCK
D5
D11
D23
PA1
XTAL
IP_B2
A6
IP_A2
PC8
D1
D7
D21
D29
PB27
IP_A4
D6
D28
D30
D31
PA2
EXTAL
IP_B0
IP_B5
A27
A23
A15
A13
D25
PB17
PB31
IP_B3
A11
IP_A1
PC9
D2
D8
D27
PB14
A31
A1
PC10 CD1#
PC13
D4
PA6
EXTCLK
IP_B7
PD4
A14
IP_A0
PC7
XFC
VDDSYN
TCKTMSTRST#TDO
VDDSYNXFCEXTCLKXTALEXTAL
GNDSRESET#
GND
3.3VCCHRESET# DSDI
DSDO
DSCK
FRZ
IP_B0
FRZ
IP_B1
3.3VCC 3.3VCC
3.3VCC
3.3VCC3.3VCC
R1210K
J2
123456
R1310K
U3
MPC860
M3M2K4
W14
W12
W11
W10
W13
W9
W7
W6
U13
T11
V11
U11
T13
V13
V10
T10
U10
T12
V9
U9
V8
U8
T9
U12
V7
T8
U7
V12
V6
W5
U6
T7
R8
R7
R6
R5
P16
F16
F4
P4
R9
R10
R11
R12
R13
R14
R15
F5
G5
H5
J5 K5
L5 N15
M15
L15
K15
J15
H15
G15
F15
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
M5
N5
P5
T14
P15
W8
M1
H19
A8
F6
F7
F8
F9
F10
F11
F12
F13
F14
G6
G7
G8
G9
G10
G11
G12
G13
G14
H6
H7
H8
H9
H10
H11
H12
H13
H14
J6 J7 J8 J9 J10
J11
J12
J13
J14
K6
K7
K8
K9
K10
K11
K12
K13
K14
L6 L7 L8 L9 L10
L11
L12
L13
L14
M6
M7
M8
M9
M10
M11
M12
M13
M14
N6
N7
N8
N9
N10
N11
N12
N13
N14
P6
P7
P8
P9
P10
P11
P12
P13
P14
U19T19R18P17P19N18M17M19L17K18J17G16F17E17D17C18U18R17N16P18N17N19L16K16L19K17J18J16F19E19D19E16C19C17
P1N1
T2
W3
N2
R1T1
U1V1
H2J3J2G1G2J4K3H1J1R4
W16U16U15V16T15W17V17W18T16R16V18V19U17B7H18V15H4
A9A11A12A10A13C10D10C11B11B10B12C12D11D9
B13C13D12A14B14C14A15B15C15D15A16B16A17B17C16A18B18B19
G4E2E1B9C9B2F1E3D2F3C2D1L3H3K1F2V3V5
W4V4G3
V14U14
W15C7A6B6A5D8C8A7B8
C4D5B4A4E4D4A2C3
D7C6B5C5B1C1D3R2P3N4P2N3L4L2M4L1
G18H17
H16
G19G17
T5T4U3W2U4U5T6T3B3A3K2R3
T17T18R19M16M18L18K19J19F18E18D18D16
BADDR28BADDR29BADDR30
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DH
VD
DL
VD
DL
VD
DL
VD
DL
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
D
CLK8/TOUT4/L1TCLKB/PA0CLK7/TIN4/BRGO4/PA1
CLK6/TOUT3/L1RCLKB/BRGCLK2/PA2CLK5/TIN3/BRGOUT3/PA3
CLK4/TOUT2/PA4CLK3/TIN2/L1TCLKA/BRGOUT2/PA5
CLK2/TOUT1/BRGCLK1/PA6CLK1/TIN1/L1RCLKA/BRGO1/PA7
L1RXDA/PA8L1TXDA/PA9
L1RXDB/PA10L1TXDB/PA11
TXD2/PA12RXD2/PA13TXD1/PA14RXD1/PA15
RSTRT1/PB14BRGO3/PB15
L1RQA/L1ST4/PB16L1RQB/L1ST3/PB17
RTS2/L1ST2/PB18RTS1/L1ST1/PB19
SMRXD2/L1CLKOA/PB20SMTXD2/L1CLKOB/PB21SMSYN2/SDACK2/PB22SMSYN1/SDACK1/PB23
PB24/SMRXD1PB25/SMTXD1
PB26/I2CSCL/BRGO2PB27/I2CSDA/BRGO1
SPIMISO/BRGO4/PB28SPIMOSI/PB29
SPICLK/PB30SPISEL/REJECT1/PB31
XTALEXTAL
XFC
CLKOUT
EXTCLK
KAPWRVDDSYN
VSSSYNVSSSYN1
IP_B0/IWP0/VFLS0IP_B1/IWP1/VFLS1
IP_B2/IOIS16_B/AT2IP_B3/IWP2/VF2IP_B4/LWP0/VF0IP_B5/LWP1/VF1IP_B6/DSDI/AT0IP_B7/PTR/AT3
ALE_B/DSCK/AT1WAIT_B
PD3/REJECT4 {TXD[1]}PD4/REJECT3 {TXD[2]}PD5/REJECT2 {TXD[3]}
PD6/RTS4 {RX_DV}PD7/RTS3 {RX_ER}
PD8/TXD4 {RX_CLK}PD9/RXD4 {TXD[0]}
PD10/TXD3 {RXD[0]}PD11/RXD3 {TX_ER}
PD12/L1SYNCB {MDC}PD13/L1TSYNCB {RXD[1]}PD14/L1RSYNCA {RXD[2]}PD15/L1TSYNCA {RXD[3]}
SPARE1 {CRS}SPARE2 {MDIO}
SPARE3 {TX_EN}SPARE4 {COL}
A31A30A29A28A27A26A25A24A23A22A21A20A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0
BRBGBBTSIZ0/REGTSIZ1RD/WRBURSTBIBDIP/GPL_B5TSTATEAASRSV/IRQ2KR/RETRY/IRQ4/SPKROUTCR/IRQ3DP0/IRQ3DP1/IRQ4DP2/IRQ5DP3/IRQ6FRZ/IRQ6IRQ0IRQ1IRQ7 {TX_EN}WE0/BS_B0/IORDWE1/BS_B1/IOWRWE2/BS_B2/PCOEWE3/BS_B3/PCWEBS_A0BS_A1BS_A2BS_A3
CS7/CE(2)BCS6/CE(1)BCS5CS4CS3CS2CS1CS0
GPL_A0/GPL_B0OE/GPL_A1/GPL_B1GPL_A2/GPL_B2/CGPL_A3/GPL_B3/CUPWAITB/GPL_B4UPWAITA/GPL_A4GPL_A5PORESETRSTCONFHRESETSRESETTEXPOP0OP1OP3/MODCK2/DSDOOP2/MODCK1/STS
TMSTDI/DSDI
TCK/DSCK
TRSTTDO/DSDO
IP_A0IP_A1
IP_A2/OIS16_AIP_A3IP_A4IP_A5IP_A6IP_A7
CE1_ACE2_AALE_A
WAIT_A
PC4/CD4/L1RSYNCAPC5/CTS4/L1TSYNCA/SDACK1
PC6/CD3/L1RSYNCBPC7/CTS3/L1TSYNCB/SDACK2
PC8/CD2/TGATE2PC9/CTS2
PC10/CD1/TGATE1PC11/CTS1
PC12/L1RQA/L1ST4PC13/L1RQB/L1ST3
PC14/DREQ1/RTS2/L1ST2PC15/DREQ0/RTS1/L1ST1
L18.2mH
+
C1210uF
C17150pF
C130.1uF
C140.1uF
C150.1uF
U4
50MHZ OSC
1
23
4 NC
GNDOUT
VCC
R61 0K01 2
J3 2X5 PIN HEADER
1 23 45 67 89 10R63 0K0
1 2
R60 0K01 2
R811K
R821K
R62 0K01 2
C16 0.1uF
12
D[0:31]2,4,6,9,10
A[0:31]2,4,9,10
BADDR[28:30]9,10
CLKOUT 4
IP_B[7:0] 6,8,10
PC[15:4] 2,6,8,9,10
PA[15:0] 6,8,10
PB[31:14] 6,8,10
PD[15:3] 6,8,10
IP_A[7:0] 6,10
RETRY#2,9,10IRQ3#6,9,10
DP22,9,10DP12,9,10
CE2_A# 6,10
RD/WR#2,9,10
TEA#2,9,10
BS_A3#4,6,9,10
BURST#2,9,10
TA#2,9,10
BS_B3#6,9,10
BS_A1#4,6,9,10
TSIZ02,9,10
BS_B1#6,9,10
HRESET#6,9,10
MODCK16,9,10
BG#2,9,10
GPL_A3#4,6,8,9,10GPL_B4#6,8,9,10
POR#8,9,10
TEXP6,8,10
IRQ7#6,9,10
CS9054#2,9,10
CSSDRAM#4,6,9,10
GPL_A1#4,6,8,9,10
OP16,8,10
ALE_B 6,8,10
IRQ0#6,9,10
CS5#6,9,10
DP02,9,10
CS7#6,9,10
GPL_A4#6,8,9,10
ALE_A 6,10
BDIP#2,9,10
IRQ2#6,9,10
DP32,9,10
TS#2,9,10
TSIZ12,9,10
BI#2,9,10
AS#6,10
BS_A0#4,6,9,10
BS_A2#4,6,9,10
CE1_A# 6,10
BS_B0#4,6,9,10
BS_B2#6,9,10
BB#2,9,10
GPL_A5#4,6,8,9,10
RESTCONF#6,10
SRESET#6,9,10
OP06,8,10
CS2#9,10
CSFLASH#4,6,9,10
GPL_A0#4,6,8,9,10
GPL_A2#4,6,8,9,10
MODCK26,9,10
BR#2,9,10
FRZ6,10
LINT#2,9,10
CS6#6,9,10
CS4#6,9,10
WAIT_B# 6,8,10
WAIT_A# 6,10
TDI6,10
TCK10TMS6,10
TDO10TRST#10
VDDSYN 10XFC 10EXTCLK 10XTAL 10EXTAL 10
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
32 PIN PLCC SOCKET
CLOCK BUFFERS
PLACE TERMINATORS AT TRACE END
MANUFACTURING OPTION (DO NOT INSTALL)
SDRAM CLOCK ENABLE/DISABLE
These Resistors are not required.
***
(no_pop)
(no_pop) (no_pop) (no_pop) (no_pop) (no_pop)
(no_pop)(no_pop)(no_pop)(no_pop)(no_pop)
*** (no_pop)
91-0002-300-A 300
SDRAM
PLX TECHNOLOGY870 Maude Ave, Sunnyvale, CA 94085
Custom
4 11Friday, July 12, 2002
WWW.PLXTECH.COMTitle
Size Document Number Rev
Date: Sheet of
APWE#RAS0#CAS0#DQM0DQM1DQM2DQM3
A31A30A29A28
A26A25
A23A22A21A20A19A18A17A16A15A14A13
GPL_A1#
A27
A24
CKESDRAM_CLK
WE#CAS0#RAS0#CSSDRAM#
DQM3
CKESDRAM_CLK
DQM2
WE#CAS0#RAS0#CSSDRAM#
CKESDRAM_CLK
DQM1
WE#CAS0#RAS0#CSSDRAM#
D7
D2
D22
D18
D29
D5
D27
D23
D20
D30
D17
D4
D26
D0
D19
D21
D16
D1
D31
D3
D6
D28
D25D24 D8
D15
D11
D14D13
D9
D12
D10
D4D3
D0D1D2
D5
D7D6
CKESDRAM_CLK
DQM0
WE#CAS0#RAS0#CSSDRAM#
CSSDRAM#
A[0:31] D[0:31]
LCLK SRAM_CLK POM2_CLK
SRAM_CLK
SDRAM_CLK
SPARE_CLK
SPARE_CLK
MA2
MA4
MA9
MA10/AP
MA7
MA3
MA1
MA5
MA6
MA0
MA8
A19A27
A18A26
A17
A25A16
A24A15
A23A14
A22A13
A21A12
A11AP
A10
A29
A28A20
A9MA11
MA[8:0]
MAA8MAA7
MA0MA1MA2MA3MA4MA5MA6MA7MA8MA9
MA11
MAA8MAA7
MA[8:0]
MAA7MAA8
MA11
MA10/AP
MA9MA8MA7MA6MA5MA4MA3MA2MA1MA0
MAA7MAA8
MA11
MA10/AP
MA9MA8MA7MA6MA5MA4MA3MA2MA1MA0
MAA7MAA8
MA11
MA10/AP
MA9MA8MA7MA6MA5MA4MA3MA2MA1MA0
CKE
MA10/AP
SDRAM_CLK
3.3VCC
5VCC3.3VCC
3.3VCC 3.3VCC 3.3VCC 3.3VCC
3.3VCC
3.3VCC
3.3VCC 3.3VCC
3.3VCC
3.3VCC
3.3VCC 3.3VCC3.3VCC
3.3VCC
U5
K4S640832D-TC1054 TSOP
SDRAM (2MX8BITX4BANK)
23242526293031323334
22
35
2581144475053
2021
19181716
39
3837
11427
394349
284154
6124652
47
1013 36
4042454851
15
A0A1A2A3A4A5A6A7A8A9
A10
A11
DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7
BA0BA1
CS#RAS#CAS#WE#
DQMH(DQM)
CLKCKE
VCC0VCC1VCC2
VCCQ0VCCQ1VCCQ2VCCQ3
VSS0VSS1VSS2
VSSQ0VSSQ1VSSQ2VSSQ3
NC0NC1NC2NC3 NC4
NC5NC6NC7NC8NC9
DQML
U8
K4S640832D-TC1054 TSOP
SDRAM (2MX8BITX4BANK)
23242526293031323334
22
35
2581144475053
2021
19181716
39
3837
11427
394349
284154
6124652
47
1013 36
4042454851
15
A0A1A2A3A4A5A6A7A8A9
A10
A11
DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7
BA0BA1
CS#RAS#CAS#WE#
DQMH(DQM)
CLKCKE
VCC0VCC1VCC2
VCCQ0VCCQ1VCCQ2VCCQ3
VSS0VSS1VSS2
VSSQ0VSSQ1VSSQ2VSSQ3
NC0NC1NC2NC3 NC4
NC5NC6NC7NC8NC9
DQML
U6
K4S640832D-TC1054 TSOP
SDRAM (2MX8BITX4BANK)
23242526293031323334
22
35
2581144475053
2021
19181716
39
3837
11427
394349
284154
6124652
47
1013 36
4042454851
15
A0A1A2A3A4A5A6A7A8A9
A10
A11
DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7
BA0BA1
CS#RAS#CAS#WE#
DQMH(DQM)
CLKCKE
VCC0VCC1VCC2
VCCQ0VCCQ1VCCQ2VCCQ3
VSS0VSS1VSS2
VSSQ0VSSQ1VSSQ2VSSQ3
NC0NC1NC2NC3 NC4
NC5NC6NC7NC8NC9
DQML
U7
K4S640832D-TC1054 TSOP
SDRAM (2MX8BITX4BANK)
23242526293031323334
22
35
2581144475053
2021
19181716
39
3837
11427
394349
284154
6124652
47
1013 36
4042454851
15
A0A1A2A3A4A5A6A7A8A9
A10
A11
DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7
BA0BA1
CS#RAS#CAS#WE#
DQMH(DQM)
CLKCKE
VCC0VCC1VCC2
VCCQ0VCCQ1VCCQ2VCCQ3
VSS0VSS1VSS2
VSSQ0VSSQ1VSSQ2VSSQ3
NC0NC1NC2NC3 NC4
NC5NC6NC7NC8NC9
DQML
R14 0K022R15 0K022R17 0K022R18 0K022R19 0K022R21 0K022R22 0K022R24 0K022
R23 33
R20 33
R27 33
R28 33
U9
CY2305
3
2
5
7
8
6
4
1
CLK1
CLK2
CLK3
CLK4
CLKOUT
VDD
GND
REFR26 33
R2951
C3022pF
R3051
C3122pF
R3151
C3222pF
R3351
C2810pF
R69 0K022R68 0K022
R760K0
R770K0
U31
74LCX257MTC
2356
11101413
151
4
7
9
12
16
8
1A1B2A2B3A3B4A4B
GA/B
1Y
2Y
3Y
4Y
VCC
GND
U32
74LCX257MTC
2356
11101413
151
4
7
9
12
16
8
1A1B2A2B3A3B4A4B
GA/B
1Y
2Y
3Y
4Y
VCC
GND
U33
74LCX257MTC
2356
11101413
151
4
7
9
12
16
8
1A1B2A2B3A3B4A4B
GA/B
1Y
2Y
3Y
4Y
VCC
GND
R250K0
R160K0
R3251
C2922pF
C3322pF
C180.1uF
12
C190.1uF
12
C200.1uF
12
C210.1uF
12
C220.1uF
12
C240.1uF
12
C250.1uF
12
C34 0.1uF
12
C26 0.1uF
12
C27 0.01uF
12
C230.1uF
12
U10AM29LV040B-90NS
222431
1314151718192021
3216
3023
2928
425232627
56789
101112
1
CEOEWE
I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7
VC
CG
ND
A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0
A18
D[0:31]2,3,6,9,10
CSFLASH#3,6,9,10
BS_A0#3,6,9,10BS_A1#3,6,9,10BS_A2#3,6,9,10BS_A3#3,6,9,10
GPL_A1#3,6,8,9,10
GPL_A3#3,6,8,9,10GPL_A2#3,6,8,9,10
CSSDRAM#3,6,9,10
GPL_A0#3,6,8,9,10
BS_B0#3,6,9,10
LCLK 2,9,10
POM2_CLK 8CLKOUT3
A[0:31]2,3,9,10
GPL_A5#3,6,8,9,10
A72,3,9,10A82,3,9,10
CKE 10
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Indicator LEDs
Power Up Configuration
OSC (f) MODCK1 MODCK2
4Mhz OSC 1 1
50Mhz OSC 1 0
Wait Control Input to UPM
***
***
***
***
***
***
***
***
(no_pop)
(no_pop)
(no_pop)
(no_pop)
(no_pop)
(no_pop)
(no_pop)
(no_pop)
(no_pop)
***
91-0002-300-A 300
RESET
PLX TECHNOLOGY780 Maude Ave, Sunnyvale, CA 94085
Custom
6 11Friday, July 12, 2002
WWW.PLXTECH.COMTitle
Size Document Number Rev
Date: Sheet of
FRZ
PC7PC6
PC4PC5
PA3
PA0
PA2PA1
PA4PA5
PA7PA6
PA10
PA8
PA11
PA9
PA15 RXDAPA14 TXDAPA13PA12
PB16PB17
PB14PB15
PB31PB30
PB28PB29
PB26PB27
PB24PB25
PB23PB22
PB20PB21
PB18PB19
PC9PC8
PC10PC11
PC13PC14
PC12
PC15
PD7
PD14
PD12PD11
PD13
PD6
PD3
PD5
PD10PD9PD8
PD4
PD15
IP_A1
IP_A3
IP_A0
IP_A2
IP_A6
IP_A4IP_A5
IP_A7
IP_B6
IP_B3IP_B2
IP_B5
IP_B7
IP_B0
IP_B4
IP_B1
MODCK1
HRESET#
MODCK2
GPL_A4#
GPL_B4#
TA#
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC3.3VCC
3.3VCC
3.3VCC
3.3VCC 3.3VCC
3.3VCC
U24
NC7SZD384P5
1
23
4 5
A
BGND
EN# VCC
U25
NC7SZD384P5
1
23
4 5
A
BGND
EN# VCC
R44
0K110
1 2
R46
0K110
12
U26
NC7SZD384P5
1
23
4 5
A
BGND
EN# VCC
R4510K
12
RN18
742-08-3-103-J-XX
1234 5
678
RN21
742-08-3-103-J-XX
1234 5
678
RN24
742-08-3-103-J-XX
1234 5
678
RN27
742-08-3-103-J-XX
1234 5
678
RN29
742-08-3-103-J-XX
1234 5
678
RN17
742-08-3-103-J-XX
1234 5
678
RN20
742-08-3-103-J-XX
1234 5
678
RN23
742-08-3-103-J-XX
1234 5
678
RN26
742-08-3-103-J-XX
1234 5
678
RN32
742-08-3-103-J-XX
1234 5
678
RN35
742-08-3-103-J-XX
1234 5
678
RN38
742-08-3-103-J-XX
1234 5
678
RN41
742-08-3-103-J-XX
1234 5
678
RN28
742-08-3-103-J-XX
1234 5
678
RN31
742-08-3-103-J-XX
1234 5
678
RN34
742-08-3-103-J-XX
1234 5
678
RN37
742-08-3-103-J-XX
1234 5
678
RN40
742-08-3-103-J-XX
1234 5
678
RN19
742-08-3-103-J-XX
1234 5
678
RN22
742-08-3-103-J-XX
1234 5
678
RN25
742-08-3-103-J-XX
1234 5
678
RN30
742-08-3-103-J-XX
1234 5
678
RN33
742-08-3-103-J-XX
1234 5
678
RN36
742-08-3-103-J-XX
1234 5
678
RN39
742-08-3-103-J-XX
1234 5
678
RN44
742-08-3-103-J-XX
1234 5
678
RN47
742-08-3-103-J-XX
1234 5
678
RN42
742-08-3-103-J-XX
1234 5
678
RN45
742-08-3-103-J-XX
1234 5
678
RN43
742-08-3-103-J-XX
1234 5
678
RN46
742-08-3-103-J-XX
1234 5
678
D1
GREEN_LED
21
D2
RED_LED
21
R38 10K1 2
R67 1K1 2
R42 10K1 2
R40 10K1 2 R41 1k
1 2
R43 1K1 2
R65 1K1 2
R64 10K1 2
R39 1K1 2
R75 1K1 2
R70 10K1 2
R74 10K1 2
R71 1K1 2
R73 1K1 2
R72 10K1 2
R66 10K1 2
U34
74LCX245MTC
23456789
191
1817161514131211
2010
A1A2A3A4A5A6A7A8
GT/R#
B1B2B3B4B5B6B7B8
VC
CG
ND
R78 1K1 2
R79 1K1 2
PA[15:0]3,8,10
IP_A[7:0]3,10
CS7#3,9,10
CS5#3,9,10CS4#3,9,10
CS6#3,9,10
USERO2,9,10
CSSDRAM#3,4,9,10CSFLASH#3,4,9,10
IP_B[7:0]3,8,10
PC[15:4]2,3,8,9,10
PB[31:14]3,8,10
IRQ3#3,9,10
SRESET#3,9,10HRESET#3,9,10
BS_A1#3,4,9,10BS_A2#3,4,9,10BS_A3#3,4,9,10
BS_A0#3,4,9,10
BS_B2#3,9,10BS_B3#3,9,10
BS_B0#3,4,9,10BS_B1#3,9,10
GPL_A0#3,4,8,9,10GPL_A1#3,4,8,9,10GPL_A2#3,4,8,9,10GPL_A3#3,4,8,9,10
GPL_B4#3,8,9,10GPL_A4#3,8,9,10GPL_A5#3,4,8,9,10
PD[15:3]3,8,10
IRQ2#3,9,10
MODCK13,9,10MODCK23,9,10
IRQ0#3,9,10IRQ7#3,9,10
CE1_A#3,10CE2_A#3,10
ALE_B3,8,10
TDI3,10
ALE_A3,10
WAIT_B#3,8,10WAIT_A#3,10
AS#3,10
FRZ3,10
OP03,8,10OP13,8,10
TEXP3,8,10
RESTCONF#3,10
TMS3,10
D72,3,4,9,10D52,3,4,9,10
D102,3,4,9,10D92,3,4,9,10
D122,3,4,9,10D112,3,4,9,10
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
PCI Edge Connector
Note:This connector is keyed for both 3.3V and 5V PCI I/O
Local Bus Power Source
Vout = 3.3V(3A)
Local Bus 3.3VCC is selectable at manufacturing (R47 or R48):Populate R47 if using 3.3V supply from the PCI connectorPopulate R48 if using 3.3V supply from the Voltage regulator (default)
1%
1%
Each power supply group pins must be tiedtogether and have bypass capacitors(+5V, +12V,-12V, and +3.3V).
Each power group has .1uF and 10uF caps.
U27 option: 1. If LT1587CM (adjustable) is used, install R49 and R50 (default). 2. If LT1587CM-3.3 is used, do not install R49 and replace R50 with a jumper.
R37 & R38 must be lessthan 0.01 ohm (R)
(no_pop)
***
91-0002-300-A 300
PCI Edge Connector
PLX TECHNOLOGY780 Maude Ave, Sunnyvale, CA 94085
Custom
7 11Friday, July 12, 2002
WWW.PLXTECH.COMTitle
Size Document Number Rev
Date: Sheet of
TDD
AD31 AD30AD29
AD28AD27 AD26AD25
AD24
AD23AD22
AD21 AD20AD19
AD18AD17 AD16
AD15AD14
AD13AD12 AD11AD10
AD9
AD8AD7
AD6AD5 AD4AD3
AD2AD1 AD0
5VCC 5VCC
+VI/O +VI/O3VCCPCI 5VCC3VCCPCI5VCC +12VCC-12VCC
3VCCPCI
5VCC
5VCC +VI/O +12VCC -12VCC3VCCPCI
3.3VCC VCC
C
TP3TP
1
C
TP5TP
1
C
TP2TP
1
C
TP1
1
C
TP4TP
1
U27LT1587CM
3
1
2VIN
AD
J
VOUT
R490K110
+ C4710uF
12
R500K180
C480.1uF1
2
+ C4610uF
12
R47 0K0
R48 0K0
+C4910uF
12
C540.1uF
12
+C5010uF
12
C550.1uF
12
+C5110uF
12
C560.1uF
12
C570.1uF
12
+C5210uF
12
+C5310uF
12
C580.1uF
12
J6
PCICONUNV
A1B1A2B2A3B3A4B4A5B5A6B6A7B7A8B8A9B9A10B10A11B11
A14B14A15B15A16B16A17B17A18B18A19B19A20B20A21B21A22B22A23B23A24B24A25B25A26B26A27B27A28B28A29B29A30B30A31B31A32B32A33B33A34B34A35B35A36B36A37B37A38B38A39B39A40B40A41B41A42B42A43B43A44B44A45B45A46B46A47B47A48B48A49B49
A52B52A53B53A54B54A55B55A56B56A57B57A58B58A59B59A60B60A61B61A62B62
TRST#-12V+12VTCKTMSGNDTDITDO+5V+5V
INTA#+5VINTC#INTB#
+5VINTD#RESERVEDPRSNT1#
VIORESERVEDRESERVEDPRSNT2#
3.3VauxRESERVEDRST#GND
VIOCLKGNT#GNDGNDREQ#
PME#VIOAD30AD31+3.3VAD29AD28GNDAD26AD27GNDAD25
AD24+3.3VIDSELC/BE3#+3.3VAD23AD22GNDAD20AD21GNDAD19
AD18+3.3VAD16AD17+3.3VC/BE2#
FRAME#GNDGNDIRDY#
TRDY#+3.3VGNDDEVSEL#
STOP#GND+3.3VLOCK#
ReservedPERR#Reserved+3.3V
GNDSERR#PAR+3.3V
AD15C/BE1#+3.3VAD14AD13GNDAD11AD12GNDAD10AD9GND
C/BE0#AD8+3.3VAD7
AD6+3.3VAD4AD5
GNDAD3AD2GNDAD0AD1VIOVIO
REQ64#ACK64#+5V+5V+5V+5V
AD[31:0]2,10
REQ#2,10
PME# 2,10
INTA# 2,10
C/BE3#2,10
C/BE2#2,10
DEVSEL#2,10
IRDY#2,10
LOCK#2,10
SERR#2,10
PERR#2,10
C/BE1#2,10
CLK 2,10
RST# 2,10
GNT# 2,10
IDSEL 2,10
FRAME# 2,10
TRDY# 2,10
STOP# 2,10
PAR# 2,10
C/BE0# 2,10
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
MPC860 BYPASS CAPS.TO POWER CONNECTOR PINS
Serial Port
Two groups of powersupply to the POM2(PLX Option Module):install correctresistors forrequired power.
Reset Circuitry
*** ***(no_pop)
(no_pop)
91-0002-300-A 300
BLOCK DIAGRAM
PLX TECHNOLOGY870 Maude Ave, Sunnyvale, CA 94085
Custom
8 11Friday, July 12, 2002
WWW.PLXTECH.COMTitle
Size Document Number Rev
Date: Sheet of
PB15PB14
PB26PB27
PB29
PB24
PB30
PB25
PB31
PB28
PB18PB19
PB21
PB16
PB22
PB17
PB23
PB20
PC11CTS1#
PC8PC9
PC4PC5
PC13
PC10CD1#
PC15RTS1#
PC7SDACK1#
PC14MDREQ1#
PC6
PC12
VCC_G1
PD10
PD5
PD15
PD3
PD14
PD4
PD8PD7
PD6
PD13
PD9
PD11PD12
IP_B0
IP_B7
IP_B4
IP_B5
IP_B1
IP_B6
IP_B2IP_B3
PA3PA4
PA2
PA11
PA9PA8PA7
PA0 BIGEND#
PA5
PA1 USERIN
PA10
PA6
PA14 TXD1PA13PA12
PA15 RXD1
RXD
CD
CTS
RTSTXDTXD1
RTS1#
CTS1#RXD1CD1#
VCC_G2
+12VCC-12VCC
3.3VCC 5VCC 3.3VCC 5VCC
3.3VCC
3.3VCC
3.3VCC
3.3VCC
R520K0
R510K0
R55 10K1 2
R5610K
12
P1
CONN DB9-MALE
594837261
U28
MAX3245
26
27
3
25
28
24
1
2
1413
910
2223
12 11
151617181920
45678
21
VCC
V+
V-
GND
C1+
C1-
C2+
C2-
T1INT2IN
T1OUTT2OUT
FORCEOFF#FORCEON
T3IN T3OUT
R5OUTR4OUTR3OUTR2OUTR1OUTR2OUTB
R1INR2INR3INR4INR5IN
INVALID#
R58 10K1 2R59 10K1 2
R57 10K1 2
+C7910uF
12
C80100nF
C84100nF
C82100nF
C810.1uF
C83100nF
+ C6810uF
12
C670.1uF
12
C700.1uF
12
R530K0
R540K0
+C6910uF
12
R3610K
12
U20
MAX6306UK30D1-T
53
1
24
VCCMR#
RESET#
GNDRST_IN
R3710K
12
SW1
SW PUSHBUTTON
J7 POM2
303132333435363738394041
50
4243444546474849
29
89
10111213141516171819202122
59
2425262728
567
1234
5152535455565758
60616263646566676869707172737475767778798081828384858687888990919293949596
10099
9798
23
PB14PB15VSSPB16PB17PB18PB19PB20PB21PB22PB23VSS
VSS
PB24PB25PB26PB27PB28PB29PB30PB31
SPARE
VSSPA0PA1PA2PA3PA4PA5PA6VSSPA7PA8PA9PA10PA11VSS
VCC_B
PA12PA13PA14PA15SPARE
GPL_B4#GPL_A5#SPARE
GPL_A4#VSSCLKVSS
PC4PC5PC6PC7PC8PC9
PC10PC11
PC12PC13PC14PC15
PD3PD4PD5PD6
VCC_APD7PD8PD9
PD10PD11PD12PD13PD14PD15IP_B0IP_B1IP_B2IP_B3IP_B4
VCC_BIP_B5IP_B6IP_B7
ALE_BWAIT_B#
TEXPOP1OP0VSS
VCC_AGPL_A0#GPL_A1#
VSS
-12VCC+12VCC
GPL_A2#GPL_A3#
VCC_A
C590.1uF
12
C600.01uF
12
C610.1uF
12
C620.01uF
12
C630.1uF
12
C640.01uF
12
C660.01uF
12
C650.1uF
12
C710.1uF
12
C740.01uF
12
C730.1uF
12
C770.1uF
12
C760.01uF
12
C780.01uF
12
C450.1uF
12
C720.01uF
12
C750.1uF
12
POM2_CLK4
PC[4:15] 2,3,6,9,10
PA[0:15]3,6,10
PB[14:31]3,6,10
PD[3:15] 3,6,10
TEXP 3,6,10
IP_B[7:0] 3,6,10
ALE_B 3,6,10WAIT_B# 3,6,10
OP0 3,6,10OP1 3,6,10
GPL_A4#3,6,9,10
GPL_A0# 3,4,6,9,10GPL_A1# 3,4,6,9,10
GPL_A2# 3,4,6,9,10GPL_A3# 3,4,6,9,10
GPL_B4#3,6,9,10GPL_A5#3,4,6,9,10
PA143,6,10PC153,6,10
PC113,6,10
PC103,6,10PA153,6,10
LRESETO#2,10
POR# 3,9,10
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Note: Place the 3 PLCC devices co-incident on the board; that is, theyshare common pins and the 20 fits inside the 44 which fits inside the68.
Prototyping Footprints
91-0002-300-A 300
BLOCK DIAGRAM
PLX TECHNOLOGY780 Maude Ave, Sunnyvale, CA 94085
Custom
9 11Friday, July 12, 2002
WWW.PLXTECH.COMTitle
Size Document Number Rev
Date: Sheet of
D24
D28D27
D29
D26
D31D30
D25
D17
D23
D2
D9
D12
D19D20
D8
D14
D16
D3D4
D6
D1D0
D11
D18
D5
D15
D7
D21
D10
D22
D13
A8
A6
A9
A21
A17
A3
A12
A15
A4
A1A0
A27
A22
A14
A5
A2
A29
A23
A20A19
A7
A11
A25
A16
A28
A30
A26
A24
A13
A18
A31
A10
FP2
44 Pin TQFP Footprint
123456789
1011
3332313029282726252423
44 43 42 41 40 39 38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22
1234567891011
3332313029282726252423
44 43 42 41 40 39 38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22
FP4
20 Pin PLCC Footprint
45678
9 10 11 12 13
3 2 1
1817161514
20 19
45678
9 10 11 12 13
3 2 1
1817161514
20 19
FP8
68 Pin PLCC Footprint
9 8 7 6 5 4 3 2 1
1011121314151617181920212223242526
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
6059585756555453525150494847464544
68 67 66 65 64 63 62 61
9 8 7 6 5 4 3 2 1
1011121314151617181920212223242526
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
6059585756555453525150494847464544
68 67 66 65 64 63 62 61
FP1
44 Pin PLCC Footprint
789
1011121314151617
18 19 20 21 22
3332313029
393837363534
44 43 42 41 406 5 4 3 2 123 24 25 26 27 28
7891011121314151617
18 19 20 21 22
3332313029
393837363534
44 43 42 41 406 5 4 3 2 123 24 25 26 27 28
FP9
44 Pin TQFP Footprint
123456789
1011
3332313029282726252423
44 43 42 41 40 39 38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22
1234567891011
3332313029282726252423
44 43 42 41 40 39 38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22
FP6
20 Pin SOIC Footprint
123456789
10
20191817161514131211
12345678910
20191817161514131211
FP5
20 Pin SOIC Footprint
123456789
10
20191817161514131211
12345678910
20191817161514131211J9
2X36 PIN HEADER
727170696867666564636261605958575655545352515049484746454443424140393837
123456789
101112131415161718192021222324252627282930313233343536
727170696867666564636261605958575655545352515049484746454443424140393837
123456789101112131415161718192021222324252627282930313233343536
J8
2X36 PIN HEADER
727170696867666564636261605958575655545352515049484746454443424140393837
123456789
101112131415161718192021222324252627282930313233343536
727170696867666564636261605958575655545352515049484746454443424140393837
123456789101112131415161718192021222324252627282930313233343536
FP3
16 Pin SOIC Footprint
12345678
161514131211109
12345678
16151413121110
9
FP7
16 Pin SOIC Footprint
12345678
161514131211109
12345678
16151413121110
9
A[0:31]2,3,4,10
D[0:31]2,3,4,6,10
IRQ7# 3,6,10
TS#2,3,10TA#2,3,10
RD/WR#2,3,10BURST#2,3,10
BDIP#2,3,10
RETRY#2,3,10TEA#2,3,10
TEST2,10POR#3,8,10
BR#2,3,10LCLK2,4,10
BG#2,3,10BB#2,3,10BI#2,3,10
TSIZ12,3,10LLOCKI#2,10
USERO2,6,10
TSIZ02,3,10
PC142,3,6,8,10
BS_B2# 3,6,10BS_B3# 3,6,10
BS_B0# 3,4,6,10BS_B1# 3,6,10
GPL_A2# 3,4,6,8,10GPL_A3# 3,4,6,8,10
GPL_A0# 3,4,6,8,10GPL_A1# 3,4,6,8,10
BS_A2# 3,4,6,10BS_A3# 3,4,6,10
BS_A1# 3,4,6,10BS_A0# 3,4,6,10
IRQ2# 3,6,10
CSFLASH# 3,4,6,10
CS9054# 2,3,10
CSSDRAM# 3,4,6,10
CS4# 3,6,10
CS6# 3,6,10CS7# 3,6,10
CS5# 3,6,10
GPL_B4# 3,6,8,10
GPL_A5# 3,4,6,8,10GPL_A4# 3,6,8,10
BIGEND#2,10
BADDR283,10
BADDR303,10BADDR293,10
IRQ3# 3,6,10
IRQ0# 3,6,10LINT# 2,3,10
DP02,3,10DP12,3,10
DP32,3,10DP22,3,10
MODCK13,6,10
SRESET#3,6,10MODCK23,6,10
HRESET#3,6,10
CS2# 3,10
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
91-0002-300-A 300
VIA
PLX TECHNOLOGY870 Maude Ave, Sunnyvale, CA 94085
Custom
10 11Friday, July 12, 2002
WWW.PLXTECH.COMTitle
Size Document Number Rev
Date: Sheet of
AD28
AD0
AD26
AD22
AD2
AD6
AD10
AD30
AD1
AD25AD24
AD3AD4
AD12
AD8
AD31
AD23
AD19AD20
AD15
AD18
AD29
AD16
AD14
AD9
AD11
AD5
AD7
AD13
AD21
AD17
AD27
BADDR29BADDR28
BADDR30
A2
A9
A23
A20
A16
A29
A13
A5
A22
A14
A12
A6
A28
A25
A11
A0
A7A8
A30
A27
A17
A21
A19
A3
A31
A24
A15
A4
A18
A10
A1
A26
D12
D19
D11
D23D22
D29
D4
D26
D5
D7
D24
D31
D13
D10
D6
D3
D14
D1
D9
D17
D27
D25
D2
D16D15
D8
D18
D28
D30
D21D20
D0
PA2PA3
PA15
PA6
PA9
PA13
PB19
PB21PB22
PB30
PB15
PB18
PB26
PB16
PB31
PB20
PC14
PC7
PC15
PC4
IP_B7
IP_B2
IP_B4
IP_B1IP_B0
IP_A3
IP_A7IP_A6IP_A5
IP_A0
IP_A4
IP_A2IP_A1
IP_B3
IP_B6IP_B5
PC6
PC8
PC5
PC10PC9
PC11PC12
PA4
PA1PA0
PA5
PA7PA8
PA14
PB17
PB14
PA11PA10
PA12
PB23
PB25PB24
PB28PB27
PB29
PD6PD7
PD12
PD9
PD11
PD3
PD14
PD10
PD5PD4
PD13
PD8
PD15
PC13
TP230VIA
TP226VIA
TP237VIA
TP233VIA
TP250VIA
TP246VIA
TP254VIA
TP242VIA
TP272VIA
TP258VIA
TP267VIA
TP262VIA
TP277VIA
TP283VIA
TP287VIA
TP280VIA
TP295VIA
TP291VIA
TP300VIA
TP298VIA
TP305VIA
TP303VIA
TP307VIA
TP302VIA
TP315VIA
TP309VIA
TP313VIA
TP311VIA
TP316VIA
TP318VIA
TP319VIA
TP317VIA
TP243VIA
TP238VIA
TP251VIA
TP247VIA
TP263VIA
TP259VIA
TP268VIA
TP273VIA
TP292VIA
TP288VIA
TP281VIA
TP284VIA
TP310VIA
TP308VIA
TP304VIA
TP306VIA
TP312VIA
TP296VIA
TP301VIA
TP314VIA
TP299VIA
TP116VIA
TP114VIA
TP139VIA
TP151VIA
TP128VIA
TP132VIA
TP147VIA
TP143VIA
TP124VIA
TP163VIA
TP158VIA
TP166VIA
TP169VIA
TP196VIA
TP176VIA
TP181VIA
TP186VIA
TP199VIA
TP191VIA
TP202VIA
TP213VIA
TP210VIA
TP207VIA
TP216VIA
TP220VIA
TP225VIA
TP224VIA
TP222VIA
TP234VIA
TP252VIA
TP248VIA
TP227VIA
TP239VIA
TP255VIA
TP278VIA
TP269VIA
TP274VIA
TP264VIA
TP293VIA
TP285VIA
TP289VIA
TP154VIA
TP150VIA
TP142VIA
TP146VIA
TP168VIA
TP165VIA
TP157VIA
TP162VIA
TP195VIA
TP190VIA
TP180VIA
TP185VIA
TP127VIA
TP118VIA
TP123VIA
TP172VIA
TP107VIA
TP73VIA
TP77VIA
TP63VIA
TP66VIA
TP58VIA
TP61VIA
TP81VIA
TP69VIA
TP47VIA
TP55VIA
TP51VIA
TP43VIA
TP33VIA
TP36VIA
TP30VIA
TP39VIA
TP17VIA
TP27VIA
TP21VIA
TP24VIA
TP11VIA
TP14VIA
TP6VIA
TP8VIA
TP85VIA
TP96VIA
TP93VIA
TP99VIA
TP89VIA
TP103VIA
TP110VIA
TP171VIA
TP179VIA
TP184VIA
TP175VIA
TP161VIA
TP189VIA
TP194VIA
TP149VIA
TP145VIA
TP153VIA
TP156VIA
TP126VIA
TP137VIA
TP122VIA
TP131VIA
TP134VIA
TP109VIA
TP102VIA
TP92VIA
TP95VIA
TP106VIA
TP112VIA
TP60VIA
TP62VIA
TP26VIA
TP29VIA
TP88VIA
TP98VIA
TP72VIA
TP84VIA
TP54VIA
TP57VIA
TP50VIA
TP46VIA
TP38VIA
TP42VIA
TP35VIA
TP32VIA
TP23VIA
TP20VIA
TP80VIA
TP65VIA
TP68VIA
TP16VIA
TP13VIA
TP10VIA
TP7VIA
TP76VIA
TP90VIA
TP78VIA
TP86VIA
TP82VIA
TP70VIA
TP64VIA
TP67VIA
TP74VIA
TP59VIA
TP49VIA
TP56VIA
TP53VIA
TP41VIA
TP34VIA
TP37VIA
TP45VIA
TP97VIA
TP87VIA
TP94VIA
TP91VIA
TP79VIA
TP101VIA
TP71VIA
TP75VIA
TP83VIA
TP140VIA
TP133VIA
TP138VIA
TP125VIA
TP144VIA
TP117VIA
TP120VIA
TP129VIA
TP203VIA
TP192VIA
TP200VIA
TP197VIA
TP182VIA
TP205VIA
TP173VIA
TP177VIA
TP187VIA
TP256VIA
TP244VIA
TP253VIA
TP249VIA
TP235VIA
TP260VIA
TP231VIA
TP240VIA
TP228VIA
TP217VIA
TP221VIA
TP211VIA
TP208VIA
TP214VIA
TP219VIA
TP223VIA
TP279VIA
TP286VIA
TP270VIA
TP265VIA
TP275VIA
TP282VIA
TP290VIA
TP294VIA
TP297VIA
TP119VIA
TP135VIA
TP152VIA
TP148VIA
TP159VIA
TP155VIA
TP108VIA
TP105VIA
TP111VIA
TP18VIA
TP31VIA
TP22VIA
TP28VIA
TP25VIA
TP48VIA
TP40VIA
TP44VIA
TP100VIA
TP52VIA
TP104VIA
TP19VIA
TP15VIA
TP12VIA
TP9VIA
AD[31:0]2,7
C/BE0#2,7C/BE1#2,7C/BE2#2,7C/BE3#2,7
TRDY#2,7IRDY#2,7STOP#2,7
FRAME#2,7DEVSEL#2,7
SERR#2,7PERR#2,7
LOCK#2,7PAR#2,7REQ#2,7INTA#2,7PME#2,7
ENUM#2
HRESET#3,6,9SRESET#3,6,9
TCK3
POR#3,8,9
TMS3,6
RESTCONF#3,6
WAIT_B#3,6,8
BADDR[28:30]3,9
D[0:31]2,3,4,6,9
PA[15:0]3,6,8
PB[31:14]3,6,8
PD[15:3]3,6,8
PC[15:4]2,3,6,8,9
IP_B[7:0]3,6,8
IP_A[7:0]3,6
CKE4
TRST#3
CS5#3,6,9CS4#3,6,9
CS7#3,6,9
TDI3,6
CS6#3,6,9
TDO3
CS2#3,9CSSDRAM#3,4,6,9CSFLASH#3,4,6,9
XFC3
CE1_A#3,6CE2_A#3,6
XTAL3
VDDSYN3
EXTAL3
EXTCLK3
ALE_A3,6WAIT_A#3,6
ALE_B3,6,8
IRQ2#3,6,9
IRQ7#3,6,9
BS_B0#3,4,6,9
FRZ3,6
AS#3,6
IRQ0#3,6,9
IRQ3#3,6,9
BS_B1#3,6,9BS_B2#3,6,9BS_B3#3,6,9
BS_A2#3,4,6,9
BS_A0#3,4,6,9
BS_A3#3,4,6,9
GPL_A0#3,4,6,8,9GPL_A1#3,4,6,8,9
BS_A1#3,4,6,9
GPL_B4#3,6,8,9GPL_A4#3,6,8,9
GPL_A3#3,4,6,8,9GPL_A2#3,4,6,8,9
GPL_A5#3,4,6,8,9
MODCK13,6,9
OP03,6,8OP13,6,8
TEXP3,6,8
MODCK23,6,9
BURST#2,3,9
LINT#2,3,9
TA#2,3,9
TS#2,3,9
BDIP#2,3,9
RD/WR#2,3,9
LRESETO#2,8LLOCKI#2,9
TEA#2,3,9
BIGEND#2,9
BR#2,3,9
USERO2,6,9
BB#2,3,9RETRY#2,3,9
PC142,3,6,8,9
BI#2,3,9
EESK2
LCLK2,4,9MODE02
EECS2
EEDO2
MODE12TEST2,9BG#2,3,9
LEDon/LEDin2
TSIZ02,3,9CS9054#2,3,9
DP12,3,9DP22,3,9
TSIZ12,3,9
DP32,3,9
DP02,3,9
CLK2,7RST#2,7GNT#2,7
IDSEL2,7
A[0:31]2,3,4,9
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Misc Parts
5VCC
RESET
PCI9054
MPC860 Peripheral Connector
3.3VCC ADDR/DATA BUS TEST CONNECTOR
UART
SDRAM
Universal PCI Connector (3.3V/5V)
GND
CONTROL SIGNAL CONNECTOR
FLASH
POWERSUPPLY
MPC860
Prototype Area
91-0002-300-A 300
LAYOUT
PLX TECHNOLOGY870 Maude Ave, Sunnyvale, CA 94085
Custom
11 11Friday, July 12, 2002
WWW.PLXTECH.COMTitle
Size Document Number Rev
Date: Sheet of
P2
93LC56B
PANEL1
PCB Bracket
P3
29LV040
SCREW1
Panel Screws
BAG1
Static Bag
SCREW2
Panel Screws
CABLE1
RS232 Cable