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HW/SW Interface HW/SW Interface ManagementManagement

thruthruAutomated Register Automated Register

SpecificationSpecification

Anupam BakshiAnupam Bakshi

Engineering DirectorEngineering Director

Agnisys Technology Pvt. Ltd.Agnisys Technology Pvt. Ltd.

ab@agnisys.usab@agnisys.us

Embedded Systems ConferenceEmbedded Systems Conference

Noida, India. 2008Noida, India. 2008

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AgendaAgenda

IntroductionIntroduction HW design processHW design process The ProblemThe Problem Possible SolutionsPossible Solutions Q&AQ&A

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IntroductionIntroduction

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SoC/FPGA designs todaySoC/FPGA designs today

Ever increasing design complexityEver increasing design complexity– IP (in-house/3IP (in-house/3rdrd party) party)

Integration : 30% of total development cycle*Integration : 30% of total development cycle*

– VerificationVerification 60% of total development effort*60% of total development effort*

Increased CostIncreased Cost– 80% cost is head-count related*80% cost is head-count related*

TTM pressuresTTM pressures– 89% of designs go over deadline by avg. 44%89% of designs go over deadline by avg. 44%

Parallel software developmentParallel software development

*Source: Spirit/NXP Dec 2007

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FPGA/SoC System overviewFPGA/SoC System overview

Device Driver, OS KernelDevice Driver, OS Kernel Creates Hardware Creates Hardware

abstractionabstraction Uses Hardware ProtocolsUses Hardware Protocols

– AMBA (AHB, APB)AMBA (AHB, APB)– OCP-IPOCP-IP– ProprietaryProprietary

HW/SW Interface

Hardware Protocol

Software API

Software Application

Configuration Registers

Hardware

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System Design ProcessSystem Design Process

HW/SW Interface

Hardware Protocol

Software API

Software Application

Configuration Registers

Hardware

Functional specification

Partitioning Integration

Correction iteration

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System Design ProcessSystem Design Process

Hardware Design

Hardware Verification

System Diagnostics/Firmware

Application Software

Spec

VHDL Programming guide or MS excel file

C/C++ Header

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Canonical Hardware SystemCanonical Hardware System

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Hardware RegistersHardware Registers Hardware contains many RegistersHardware contains many Registers

– 100s : Control applications100s : Control applications– 1000s : Image Processing applications1000s : Image Processing applications

Registers Used for Registers Used for – ConfigurationsConfigurations– ControlControl– StatusStatus

Why focus on Registers?Why focus on Registers?– Ubiquitous and essentialUbiquitous and essential– Wide spread impact/ Quick ROIWide spread impact/ Quick ROI– Low hanging fruit!Low hanging fruit!– Effects not just the hardware but software, firmware, Effects not just the hardware but software, firmware,

……

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The ProblemThe Problem

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The Domino effect in HW The Domino effect in HW designdesign

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The problemThe problem

Many representations of the same Many representations of the same register informationregister information– Functional SpecificationFunctional SpecificationMS Word/FrameMS Word/Frame– HW Design HW Design VHDL/VerilogVHDL/Verilog– HW Programming GuideHW Programming Guide MS MS

Word/ExcelWord/Excel– Verification Environment Verification Environment HVL/TCLHVL/TCL– FirmwareFirmware C/C++ headerC/C++ header– DiagnosticsDiagnostics C/C++ headerC/C++ header– Application SoftwareApplication Software C/C++ headerC/C++ header

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Problem Description Problem Description (contd.)(contd.)

Problems with Register Problems with Register descriptions in multiple places: descriptions in multiple places: – Time consuming to createTime consuming to create– Additions/Changes are problematicAdditions/Changes are problematic– Error proneError prone– Monotonous workMonotonous work

Longer debug timeLonger debug time Longer Hardware/Software Longer Hardware/Software

integration times.integration times.

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Problem Description Problem Description (contd.)(contd.)

1.1. Number of register is largeNumber of register is large

2.2. Changes are inevitable during Changes are inevitable during design processdesign process

– Add/remove registersAdd/remove registers– Register definition/bit fieldsRegister definition/bit fields– Register locationRegister location– Register type (r, r/w, w1c, …)Register type (r, r/w, w1c, …)– Register implementationRegister implementation

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Possible SolutionsPossible Solutions

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What if we have …What if we have …

One specification for all registersOne specification for all registers All representations generated from All representations generated from

the single sourcethe single source

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Possible solutionsPossible solutions

Single description for all registersSingle description for all registers– SPIRITSPIRIT– SystemRDLSystemRDL

ImplementationImplementation– GUI based toolsGUI based tools– Eclipse based toolsEclipse based tools– Editor based toolsEditor based tools

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SPIRITSPIRIT

Unified set of specification based on IP Unified set of specification based on IP meta-datameta-data– www.spiritconsortium.orgwww.spiritconsortium.org

Called IP-XACTCalled IP-XACT– XML SchemaXML Schema– Language neutralLanguage neutral

Comprehensive dataComprehensive data– Components, Components, RegistersRegisters, Address spaces, , Address spaces,

……– Bus definitions, Ports, …Bus definitions, Ports, …

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SPIRIT Register descriptionSPIRIT Register description

<spirit:register> <spirit:name>status</spirit:name> <spirit:description>Status register</spirit:description> <spirit:addressOffset>0x4</spirit:addressOffset> <spirit:size>32</spirit:size> <spirit:volatile>true</spirit:volatile> <spirit:access>read-only</spirit:access> <spirit:field> <spirit:name>dataReady</spirit:name> <spirit:description>Indicates that new data is available in the receiver holding register </spirit:description> <spirit:bitOffset>0</spirit:bitOffset> <spirit:bitWidth>1</spirit:bitWidth> <spirit:access>read-only</spirit:access> </spirit:field> <spirit:field> <!-- … --> </spirit:field></spirit:register>

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SystemRDLSystemRDL

Open specificationOpen specification– www.denali.comwww.denali.com

TextualTextual non-XML basednon-XML based New languageNew language Donated to SpiritDonated to Spirit

Reg chip1 { name = “some reg”; desc = “some desc”; field { hw = w; sw = r} f1[7:0] = 8’d5; field { hw = r; sw = w} f2[15:8] = 8’d10; …}Addresmap blk1_admap { name = “blk1 address map in chip1”; chip1 chip1_reg @0x0000;}

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Automation

Automation in System Automation in System DesignDesign

Hardware Design

Hardware Verification

System Diagnostics/Firmware

Application Software

Register Spec

RTL

C/C++ Header

DocumentationProgrammer’s guideMemory map

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Automation in System Design Automation in System Design (contd.)(contd.)

Register Spec

Synthesizable RTL

Documentation (HTML/Word)

C/C++ Header

Verification tests

C++ Classes

Diagnostic tests

Mnemonic/hex address mapping

Auto

Future Generators

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Benefits of Auto Register Benefits of Auto Register generationgeneration

FastFast ConsistentConsistent Correct by constructionCorrect by construction Standardized VHDL and C++ codeStandardized VHDL and C++ code Complete, in-sync documentationComplete, in-sync documentation Automatic register R/W tests Automatic register R/W tests Helps reusabilityHelps reusability

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C/C++ Header fileC/C++ Header file

typedef struct { typedef struct { union { union { Newman_ColdfireInterface_s s; Newman_ColdfireInterface_s s; hwi_uint32 filler[0x200]; hwi_uint32 filler[0x200]; } } ColdfireInterfaceColdfireInterface; ; union { union { reusememblock_s s; reusememblock_s s; hwi_uint32 filler[0x200]; hwi_uint32 filler[0x200]; } } reusememblockreusememblock; ; union { union { Newman_FrameBuffers_s s; Newman_FrameBuffers_s s; hwi_uint32 filler[0x200]; hwi_uint32 filler[0x200]; } } FrameBuffersFrameBuffers; ; union { union { Newman_genlock_s s; Newman_genlock_s s; hwi_uint32 filler[0x200]; hwi_uint32 filler[0x200]; } } genlockgenlock; ; union { union { Newman_VideoCapture_s s; Newman_VideoCapture_s s; hwi_uint32 filler[0x200]; hwi_uint32 filler[0x200]; } } VideoCaptureVideoCapture; ; :: ::

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HTML outputHTML output

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ConclusionConclusion

Manually creating multiple views of Manually creating multiple views of registers is inefficient.registers is inefficient.

Automation enables us to maintain a Automation enables us to maintain a single source of register specification.single source of register specification.

Automation streamlines the whole Automation streamlines the whole process with better process with better Hardware/Software Integration, Hardware/Software Integration, Diagnostics and VerificationDiagnostics and Verification

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Q/AQ/A