FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Topics

Bus interfaces. Platform FPGAs.

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Bus interfaces

Requirements:– High performance.– Variable signal environment.

Techniques:– Asynchronous logic.– Handshaking-oriented protocols.

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Timing diagrams

a

b

c

stable

0 1

changing

Timing constraint

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Asynchronous logic

Distribute timing information with values.– No global clock.

Clock signal paths must have the same delay as data values.

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Latching an asynchronous signal

D Qadrs

adrs_ready

adrs

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Asynchronous timing constraints

Must satisfy setup, hold times.

adrs

Setup timeHold time

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Bus system design

Requirements:– Imposed by the other side of the system.

Constraints:– Imposed by this side of the system.

a b

requirements

constraints

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

ba

Views of the bus

Hardware:

D Q D Q

Combinationallogic

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Views of bus system, cont’d.

Timing diagram:

ba

D Q D Q

Combinationallogic

x

y

x y

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Bus protocols

Basic transaction:– four-cycle handshake.

a

b

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Handshake machine

Each side is an FSM (possibly asynchronous):

a b0 1

Go

ackack

enq

0 1

enq

ack

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Basic protocols

Handshake transmits data:

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Box 1 logic

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Box 2 logic

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Bus timing

td1 = d stable

td2 = d not stable

tc1 = c rises

tc2 = c falls

tack1 = ack rises

t1 = tc1 - td1 >= tr

t2 = tack1 - tc1 >= th

t3 = tc2 - tack1 >= th

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Busses and systems

Microprocessor systems often have several busses running at different rates:

CPU

bridge

mem

I/O

High-speed

Low-speed

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Basic signals in a bus

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Bus characteristics

Physical– Connector size, etc.

Electrical– Voltages, currents, timing.

Protocol– Sequence of events.

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Advanced transactions

Multi-cycle transfers:– Several values on one handshake.– May use implicit addressing.

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

PCI bus

Used for box-level system interconnect. Two versions:

– 33 MHz.– 66 MHz.

Supports advanced transactions.

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

PCI bus read

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Multi-rate systems

Logic blocks running at different clock rates may communicate:– Multi-chip.– Single-chip.

» Slow bus connects to fast logic.

Logic 1 Logic 2

100 MHz 33 MHz

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Metastability

Registers capturing transitioning signals may take an arbitrarily long time to settle.

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Resynchronization

Use cascaded registers to minimize the chance of using a metastable value.

D Q D Qd dout

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Platform FPGAs

Put all the logic for a system on one FPGA. Requires large FPGAs plus:

– Specialized logic:» I/O support;

» memory interface.

– CPUs.

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Example: Virtex II Pro

Major features:– Large FPGA fabric.– High-speed I/O.– PowerPC.

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Virtex II Pro High-speed I/O

Rocket I/O:– parallel/serial or serial/parallel transceiver.

Clock recovery circuitry. Transceivers for multiple standards: Gigabit

Ethernet, Fibre Channel, etc. Programmable decoding features. Interface to FPGA fabric.

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Virtex II Pro CPUs

Up to 4 PowerPC 405s per chip:– 5 stage pipe, static branch prediction, etc.

Separate instruction, data caches. MMU. Timers. Scan-based debug support.

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

PowerPC CoreConnect

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Altera Stratix

Combines FPGA fabric, memory blocks, multipliers.

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Stratix DSP block