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EE1411

Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

Designing CombinationalDesigning CombinationalLogic CircuitsLogic Circuits

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolić

November 2002.

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Combinational vs. Sequential LogicCombinational vs. Sequential Logic

Combinational Sequential

Output = f(In) Output = f(In, Previous In)

CombinationalLogicCircuit

OutInCombinational

LogicCircuit

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Static CMOS CircuitStatic CMOS Circuit

At every point in time (except during the switching transients) each gate output is connected to eitherVDD or Vss via a low-resistive path.

The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).

This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

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Static Complementary CMOSStatic Complementary CMOSVDD

F(In1,In2,…InN)

In1In2

In1In2InN

PMOS only

NMOS only

PUN and PDN are dual logic networks

……

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NMOS Transistors NMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high

Y = X if A and B

B Y = X if A OR B

NMOS Transistors pass a “strong” 0 but a “weak” 1

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PMOS Transistors PMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection

Y = X if A AND B = A + B

B Y = X if A OR B = AB

PMOS Transistors pass a “strong” 1 but a “weak” 0

PMOS switch closes when switch control input is low

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Threshold DropsThreshold DropsVDD

VDD → 0PDN

0 → VDD

0 → VDD - VTn

VDD → |VTp|

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Complementary CMOS Logic StyleComplementary CMOS Logic Style

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Example Gate: NANDExample Gate: NAND

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Example Gate: NORExample Gate: NOR

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Complex CMOS GateComplex CMOS Gate

OUT = D + A • (B + C)

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Constructing a Complex GateConstructing a Complex Gate

(a) pull-down network

SN1 SN4

(b) Deriving the pull-up networkhierarchically by identifyingsub-nets

VDD VDD

(c) complete gate

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Cell DesignCell Design

Standard CellsGeneral purpose logicCan be synthesizedSame height, varying width

Datapath CellsFor regular, structured designs (arithmetic)Includes some wiring in the cellFixed height and width

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Standard Cell Layout Methodology Standard Cell Layout Methodology ––1980s1980s

signals

Routingchannel

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Standard Cell Layout Methodology Standard Cell Layout Methodology ––1990s1990s

No Routingchannels VDD

Mirrored Cell

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Standard CellsStandard Cells

Cell boundary

N WellCell height 12 metal tracksMetal track is approx. 3λ + 3λPitch = repetitive distance between objects

Cell height is “12 pitch”

Rails ~10λ

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In Out

With silicided diffusion

With minimaldiffusionrouting

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2-input NAND gate

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Stick DiagramsStick Diagrams

Contains no dimensionsRepresents relative positions of transistors

Inverter

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Stick DiagramsStick Diagrams

X = C • (A + B)

PDNABC

Logic Graph

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Two Versions of C Two Versions of C •• (A + B)(A + B)

CA B A B C

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Consistent Euler PathConsistent Euler Path

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OAI22 Logic GraphOAI22 Logic Graph

X = (A+B)•(C+D)

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Example: x = Example: x = abab++cdcd

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}

(c) stick diagram for ordering {a b c d}b

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MultiMulti--Fingered TransistorsFingered TransistorsOne finger Two fingers (folded)

Less diffusion capacitance

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Properties of Complementary CMOS Gates Properties of Complementary CMOS Gates SnapshotSnapshot

High noise margins: VOH and VOL are at VDD and GND, respectively.

No static power consumption:There never exists a direct path between VDD and VSS (GND) in steady-state mode.

Comparable rise and fall times:(under appropriate sizing conditions)

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CMOS PropertiesCMOS PropertiesFull rail-to-rail swing; high noise marginsLogic levels not dependent upon the relative device sizes; ratiolessAlways a path to Vdd or Gnd in steady state; low output impedanceExtremely high input resistance; nearly zero steady-state input currentNo direct path steady state between power and ground; no static power dissipationPropagation delay function of load capacitance and resistance of transistors

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Switch Delay ModelSwitch Delay Model

Rn Cint

NAND2 INV NOR2

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Input Pattern Effects on DelayInput Pattern Effects on Delay

Delay is dependent on the pattern of inputsLow to high transition

both inputs go low– delay is 0.69 Rp/2 CL

one input goes low– delay is 0.69 Rp CL

High to low transitionboth inputs go high

– delay is 0.69 2Rn CL

Rn Cint

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Delay Dependence on Input PatternsDelay Dependence on Input Patterns

0 100 200 300 400

A=B=1→0

A=1, B=1→0

A=1 →0, B=1

time [ps]

81A= 1→0, B=1

80A=1, B=1→0

45A=B=1→0

61A= 0→1, B=1

64A=1, B=0→1

67A=B=0→1

Delay(psec)

Input DataPattern

NMOS = 0.5μm/0.25 μmPMOS = 0.75μm/0.25 μmCL = 100 fF

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Transistor SizingTransistor Sizing

Rn Cint

EE14132

Transistor Sizing a Complex Transistor Sizing a Complex CMOS GateCMOS Gate

OUT = D + A • (B + C)

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FanFan--In ConsiderationsIn Considerations

Distributed RC model(Elmore delay)

tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

Propagation delay deteriorates rapidly as a function of fan-in –quadratically in the worst case.

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ttpp as a Function of Fanas a Function of Fan--InIn

fan-in

Gates with a fan-in greater than 4 should be avoided.

2 4 6 8 10 12 14 16

quadratic

linear

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ttpp as a Function of Fanas a Function of Fan--OutOut

2 4 6 8 10 12 14 16

tpNOR2

eff. fan-out

All gates have the same drive current.

tpNAND2

Slope is a function of “driving strength”

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ttpp as a Function of Fanas a Function of Fan--In and FanIn and Fan--OutOut

Fan-in: quadratic due to increasing resistance and capacitanceFan-out: each additional fan-out gate adds two gate capacitances to CL

tp = a1FI + a2FI2 + a3FO

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Fast Complex Gates:Fast Complex Gates:Design Technique 1Design Technique 1

Transistor sizingas long as fan-out capacitance dominates

Progressive sizing

InN CL

MNDistributed RC line

M1 > M2 > M3 > … > MN(the fet closest to theoutput is the smallest)

Can reduce delay by more than 20%; decreasing gains as technology shrinks

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Transistor ordering

critical path critical path

charged1

0→1charged

charged1

delay determined by time to discharge CL, C1 and C2

delay determined by time to discharge CL

0→1 charged

discharged

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Fast Complex Gates:Fast Complex Gates:Design Technique 3Design Technique 3Alternative logic structures

F = ABCDEFGH

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Isolating fan-in from fan-out using buffer insertion

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Reducing the voltage swing

linear reduction in delayalso reduces power consumption

But the following gate is much slower!Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design)

tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )

= 0.69 (3/4 (CL Vswing)/ IDSATn )

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Sizing Logic Paths for SpeedSizing Logic Paths for Speed

Frequently, input capacitance of a logic path is constrainedLogic also has to drive some capacitanceExample: ALU load in an Intel’s microprocessor is 0.5pFHow do we size the ALU datapath to achieve maximum speed?We have already solved this for the inverter chain – can we generalize it for any type of logic?

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Buffer ExampleBuffer Example

( )∑=

⋅+=N

iiii fgpDelay

For given N: Ci+1/Ci = Ci/Ci-1To find N: Ci+1/Ci ~ 4How to generalize this to any logic path?

In Out

(in units of τinv)

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Logical EffortLogical Effort

( )fgpCCCRkDelay

Lunitunit

⎟⎟⎠

⎞⎜⎜⎝

⎛+⋅=

p – intrinsic delay (3kRunitCunitγ) - gate parameter ≠ f(W)g – logical effort (kRunitCunit) – gate parameter ≠ f(W)f – effective fanout

Normalize everything to an inverter:ginv =1, pinv = 1

Divide everything by τinv(everything is measured in unit delays τinv)Assume γ = 1.

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Delay in a Logic GateDelay in a Logic Gate

Gate delay:d = h + p

effort delay intrinsic delay

Effort delay:

h = g f

logical effort

effective fanout = Cout/Cin

Logical effort is a function of topology, independent of sizingEffective fanout (electrical effort) is a function of load/gate size

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Inverter has the smallest logical effort and intrinsic delay of all static CMOS gatesLogical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same currentLogical effort increases with the gate complexity

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Logical EffortLogical EffortLogical effort is the ratio of input capacitance of a gate to the inputcapacitance of an inverter with the same output current

g = 1 g = 4/3 g = 5/3

VDDVDD

Inverter 2-input NAND 2-input NOR

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Logical Effort of GatesLogical Effort of Gates

Fan-out (h)

1 2 3 4 5 6 7

pINVtpNAND

F(Fan-in)

g =p =d =

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Fan-out (h)

1 2 3 4 5 6 7

pINVtpNAND

F(Fan-in)

g = 1p = 1d = h+1

g = 4/3p = 2d = (4/3)h+2

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Intrinsic�Delay

EffortDelay

1 2 3 4 5Fanout f

Inverter:

g = 1; p = 12-i

NAND: g = 4/

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Add Branching EffortAdd Branching Effort

Branching effort:

pathon

pathoffpathonC

−− +=

EE14152

Multistage NetworksMultistage Networks

Stage effort: hi = gifiPath electrical effort: F = Cout/Cin

Path logical effort: G = g1g2…gN

Branching effort: B = b1b2…bN

Path effort: H = GFB

Path delay D = Σdi = Σpi + Σhi

( )∑=

⋅+=N

iiii fgpDelay

EE14153

Optimum Effort per StageOptimum Effort per Stage

When each stage bears the same effort:

N Hh =

( ) PNHpfgD Niii +=+= ∑ /1ˆ

Minimum path delay

Effective fanout of each stage: ii ghf =

Stage efforts: g1f1 = g2f2 = … = gNfN

EE14154

Optimal Number of StagesOptimal Number of StagesFor a given load, and given input capacitance of the first gateFind optimal number of stages and optimal sizing

invN NpNHD += /1

( ) 0ln /1/1/1 =++−=∂∂

invNNN pHHH

NHh ˆ/1=Substitute ‘best stage effort’

EE14155

From Sutherland, Sproull

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Example: Optimize PathExample: Optimize Path

Effective fanout, F =G = H =h =a =b =

g = 1f = a

g = 5/3f = b/a

g = 5/3f = c/b

g = 1f = 5/c

EE14157

Example: Optimize PathExample: Optimize Path1

g = 1f = a

g = 5/3f = b/a

g = 5/3f = c/b

g = 1f = 5/c

Effective fanout, F = 5G = 25/9H = 125/9 = 13.9h = 1.93a = 1.93b = ha/g2 = 2.23c = hb/g3 = 5g4/f = 2.59

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Example: Optimize PathExample: Optimize Path

Effective fanout, H = 5G = 25/9F = 125/9 = 13.9f = 1.93a = 1.93b = fa/g2 = 2.23c = fb/g3 = 5g4/f = 2.59

g1 = 1 g2 = 5/3 g3 = 5/3 g4 = 1

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Example Example –– 88--input ANDinput AND

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Method of Logical EffortMethod of Logical Effort

Compute the path effort: F = GBHFind the best number of stages N ~ log4FCompute the stage effort f = F1/N

Sketch the path with this number of stagesWork either from either end, find sizes: Cin = Cout*g/f

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

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SummarySummary

Sutherland,SproullHarris

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Ratioed Ratioed LogicLogic

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RatioedRatioed LogicLogic

PDNIn1In2In3

RLLoad

In1In2In3

PDNIn1In2In3

Resistive DepletionLoad

PMOSLoad

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

VT < 0

Goal: to reduce the number of devices over complementary CMOS

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RatioedRatioed LogicLogicVDD

PDNIn1In2In3

RLLoadResistive

N transistors + Load

• VOH = VDD

• VOL = RPN

RPN + RL

• Assymetrical response

• Static power consumption

• tpL= 0.69 RLCL

EE14165

Active LoadsActive LoadsVDD

In1In2In3

PDNIn1In2In3

DepletionLoad

PMOSLoad

depletion load NMOS pseudo-NMOS

VT < 0

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PseudoPseudo--NMOSNMOS

A B C D

VOH = VDD (similar to complementary CMOS)

kn VDD VTn–( )VOLVOL

2-------------–

⎝ ⎠⎜ ⎟⎛ ⎞ kp

2------ VDD VTp–( )

VOL VDD VT–( ) 1 1kpkn------–– (assuming that VT VTn VTp )= = =

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

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PseudoPseudo--NMOS VTCNMOS VTC

0.0 0.5 1.0 1.5 2.0 2.50.0

Vin [V]

W/Lp = 4

W/Lp = 2

W/Lp = 1

W/Lp = 0.25

W/Lp = 0.5

EE14168

Improved LoadsImproved Loads

A B C D

M1M2 M1 >> M2Enable

Adaptive Load

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Improved Loads (2)Improved Loads (2)VDD

Differential Cascode Voltage Switch Logic (DCVSL)

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DCVSL ExampleDCVSL Example

XOR-NXOR gate

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DCVSL Transient ResponseDCVSL Transient Response

0 0.2 0.4 0.6 0.8 1.0-0.5

Time [ns]

[V] A B

A,BA,B

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PassPass--TransistorTransistorLogicLogic

EE14173

PassPass--Transistor LogicTransistor LogicIn

puts Switch

Network

OutOut

• N transistors• No static consumption

EE14174

Example: AND GateExample: AND Gate

F = AB

EE14175

NMOSNMOS--Only LogicOnly Logic

0.5μm/0.25μm0.5μm/0.25μm

1.5μm/0.25μm

0 0.5 1 1.5 20.0

Time [ns]Vo

lt age

EE14176

NMOSNMOS--only Switchonly Switch

A = 2.5 V

C = 2.5V

A = 2.5 V

C = 2.5 V

Threshold voltage loss causesstatic power consumption

VB does not pull up to 2.5V, but 2.5V -VTN

NMOS has higher threshold than PMOS (body effect)

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NMOS Only Logic: NMOS Only Logic: Level Restoring TransistorLevel Restoring Transistor

VDDVDDLevel Restorer

• Advantage: Full Swing• Restorer adds capacitance, takes away pull down current at X• Ratio problem

EE14178

Restorer SizingRestorer Sizing

0 100 200 300 400 5000.0

W/Lr =1.0/0.25 W/Lr =1.25/0.25

W/Lr =1.50/0.25

W/Lr =1.75/0.25

t ag e

Time [ps]

3.0•Upper limit on restorer size•Pass-transistor pull-downcan have several transistors in stack

EE14179

Solution 2: Single Transistor Pass Gate with Solution 2: Single Transistor Pass Gate with VVTT=0=0

0V 2.5V

WATCH OUT FOR LEAKAGE CURRENTS

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Complementary Pass Transistor LogicComplementary Pass Transistor Logic

B B B B

F=A⊕ΒÝ

OR/NOR EXOR/NEXORAND/NAND

Pass-TransistorNetwork

Inverse

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Solution 3: Transmission GateSolution 3: Transmission Gate

C = 0 V

A = 2.5 V

C = 2.5 V

EE14182

Resistance of Transmission GateResistance of Transmission Gate

2.5 VRn

0.0 1.0 2.00

Vout, V

Rn || Rp

EE14183

PassPass--Transistor Based MultiplexerTransistor Based Multiplexer

In1 In2S S

EE14184

Transmission Gate XORTransmission Gate XOR

EE14185

Delay in Transmission Gate NetworksDelay in Transmission Gate Networks

V1 Vi-1

2.5 2.5

Vi Vi+1

Vn-1 Vn

V1 Vi Vi+1

Vn-1 Vn

InReqReq Req Req

Req Req

EE14186

Delay OptimizationDelay Optimization

EE14187

Transmission Gate Full AdderTransmission Gate Full Adder

Sum Generation

Carry Generation

Similar delays for sum and carry

EE14188

Dynamic LogicDynamic Logic

EE14189

Dynamic CMOSDynamic CMOS

In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.

fan-in of n requires 2n (n N-type + n P-type) devices

Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.

requires on n + 2 (n+1 N-type + 1 P-type) transistors

EE14190

Dynamic GateDynamic Gate

In2 PDNIn3

ClkOut

Two phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)

EE14191

Dynamic GateDynamic Gate

In2 PDNIn3

ClkOut

Two phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)

((AB)+C)

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Conditions on OutputConditions on Output

Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.Inputs to the gate can make at most one transition during evaluation.

Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

EE14193

Properties of Dynamic GatesProperties of Dynamic GatesLogic function is implemented by the PDN only

number of transistors is N + 2 (versus 2N for static complementary CMOS)

Full swing outputs (VOL = GND and VOH = VDD)Non-ratioed - sizing of the devices does not affect the logic levelsFaster switching speeds

reduced load capacitance due to lower input capacitance (Cin)reduced load capacitance due to smaller output loading (Cout)no Isc, so all the current provided by PDN goes into discharging CL

EE14194

Properties of Dynamic GatesProperties of Dynamic GatesOverall power dissipation usually higher than static CMOS

no static current path ever exists between VDD and GND (including Psc)no glitchinghigher transition probabilitiesextra load on Clk

PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn

low noise margin (NML)Needs a precharge/evaluate clock

EE14195

Issues in Dynamic Design 1: Issues in Dynamic Design 1: Charge LeakageCharge Leakage

ClkOut

Leakage sources

Precharge

Evaluate

Dominant component is subthreshold current

EE14196

Solution to Charge LeakageSolution to Charge Leakage

Same approach as level restorer for pass-transistor logic

Keeper

EE14197

Issues in Dynamic Design 2: Issues in Dynamic Design 2: Charge SharingCharge Sharing

Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness

EE14198

Charge Sharing ExampleCharge Sharing Example

CL=50fF

B B B !B

Ca=15fF

Cc=15fF

Cb=15fF

Cd=10fF

EE14199

Charge SharingCharge Sharing

CLVDD CLVout t( ) Ca VDD VTn VX( )–( )+=

ΔVout Vout t( ) VDD–CaCL-------- VDD VTn VX( )–( )–= =

ΔVout VDDCa

Ca CL+----------------------

⎝ ⎠⎜ ⎟⎛ ⎞

case 1) if ΔVout < VTn

case 2) if ΔVout > VTnB = 0

Clk Me

EE141100

Solution to Charge RedistributionSolution to Charge Redistribution

OutMkp

Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

EE141101

Issues in Dynamic Design 3: Issues in Dynamic Design 3: BackgateBackgate CouplingCoupling

Out1Mp

Dynamic NAND Static NAND

EE141102

BackgateBackgate Coupling EffectCoupling Effect

0 2 4 6

Time, ns

EE141103

Issues in Dynamic Design 4: Clock Issues in Dynamic Design 4: Clock FeedthroughFeedthrough

Coupling between Out and Clk input of the prechargedevice due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.

EE141104

Clock Clock FeedthroughFeedthrough

0 0.5 1

In &Clk

Time, ns

Clock feedthrough

EE141105

Other EffectsOther Effects

Capacitive couplingSubstrate couplingMinority charge injectionSupply noise (ground bounce)

EE141106

Cascading Dynamic GatesCascading Dynamic Gates

Out1In

Out2 ΔV

Only 0 → 1 transitions allowed at inputs!

EE141107

Domino LogicDomino Logic

In2 PDNIn3

Clk Out1

In4 PDNIn5

ClkOut2

1 → 11 → 0

0 → 00 → 1

EE141108

Why Domino?Why Domino?

Ini PDNInj

IniInj

PDN Ini PDNInj

Ini PDNInj

Like falling dominos!

EE141109

Properties of Domino LogicProperties of Domino Logic

Only non-inverting logic can be implementedVery high speed

static inverter can be skewed, only L-H transitionInput capacitance reduced – smaller logical effort

EE141110

Designing with Domino LogicDesigning with Domino Logic

In1In2

Inputs = 0during precharge

Can be eliminated!

EE141111

Footless DominoFootless Domino

The first gate in the chain needs a foot switchPrecharge is rippling – short-circuit currentA solution is to delay the clock for each stage

Clk Mp

InnIn3

0 1 0 1 0 1

1 0 1 0

EE141112

Differential (Dual Rail) DominoDifferential (Dual Rail) Domino

ClkOut = AB

MkpClk

Out = ABMkp Mp

Solves the problem of non-inverting logic

1 0 1 0

EE141113

npnp--CMOSCMOS

In2 PDNIn3

Clk Out1

In4 PUNIn5

Out2(to PDN)

1 → 11 → 0

0 → 00 → 1

Only 0 → 1 transitions allowed at inputs of PDN Only 1 → 0 transitions allowed at inputs of PUN

EE141114

NORA LogicNORA Logic

In2 PDNIn3

Clk Out1

In4 PUNIn5

Out2(to PDN)

1 → 11 → 0

0 → 00 → 1

to otherPDN’s

to otherPUN’s

WARNING: Very sensitive to noise!

Digital Integrated Circuits - UBIrboucho/me/downloads_temporarios/Rabaey...Digital Integrated...

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