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Transcript of © Digital Integrated Circuits 2nd Sequential Circuits Designing Sequential Logic Circuits Jan M....
© Digital Integrated Circuits2nd
Sequential Circuits
Designing SequentialDesigning SequentialLogic CircuitsLogic Circuits
Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic
© Digital Integrated Circuits2nd
Sequential Circuits
Sequential LogicSequential Logic
CombinationalLogic
State
Clock
Next StateCurrent State
Inputs Outputs
2 storage mechanisms:• positive feedback• charge-based
© Digital Integrated Circuits2nd
Sequential Circuits
Naming ConventionsNaming Conventions
In the text: a latch is level sensitive a register is edge-triggered
Many different naming conventions: flip-flops (level or edge?) Transparency? Dual edge/level
© Digital Integrated Circuits2nd
Sequential Circuits
Latch versus RegisterLatch versus Register Latch- stores if clock is low
transparent if clock is high
D
Clk
Q D
Clk
Q
Register- stores if clock rises, never transparent (mostly)
Clk Clk
D D
Q Q
© Digital Integrated Circuits2nd
Sequential Circuits
Latch-Based DesignLatch-Based Design
• N latch is transparentwhen = 0
• P latch is transparent when = 1
NLatch
Logic
Logic
PLatch
© Digital Integrated Circuits2nd
Sequential Circuits
Timing DefinitionsTiming Definitions
t
CLK
t
D
tc lk2q
tholdtsetup
t
Q DATASTABLE
DATASTABLE
Register
CLK
D Q
© Digital Integrated Circuits2nd
Sequential Circuits
Maximum Clock FrequencyMaximum Clock Frequency
Reg
iste
r
LOGIC
tP(comb)
Timing Constraints:tclk2q + tp(comb) + tsetup = Ttcdreg + tcdlogic > thold
First Constraint ensures clock is slow
enough that Registers sample
correct value
Second Constraint ensures that there
is no path after the clock changes to
alter the previously stored data
© Digital Integrated Circuits2nd
Sequential Circuits
Positive Feedback: Bi-StabilityPositive Feedback: Bi-Stability
Vi1
A
C
B
Vo2
Vi1=Vo2
Vo1 Vi2
Vi2=Vo1
A,B Stable pointsC is unstable:(metastable)Feedback moves state toStable points, eventually
© Digital Integrated Circuits2nd
Sequential Circuits
Writing a Static LatchWriting a Static Latch
D
CLK
CLK
D
Use the clock to distinguish between the transparent and opaque states
Converting into a MUXForcing the state(can implement as NMOS-only)
© Digital Integrated Circuits2nd
Sequential Circuits
Mux-Based LatchesMux-Based LatchesNegative latch(transparent when CLK= 0)
Positive latch(transparent when CLK= 1)
CLK
1
0D
Q
InClkQClkQ InClkQClkQ
0
CLK
1D
Q
© Digital Integrated Circuits2nd
Sequential Circuits
Master-Slave RegisterMaster-Slave Register
Two opposite latches trigger on edgeAlso called master-slave latch pair
CLK
D
Qm
Q
QQm
D
CLK
CLK
© Digital Integrated Circuits2nd
Sequential Circuits
Clk-Q DelayClk-Q Delay
CLK
D
Q
Tclk-q Tclk-q
Clock to Q delays areDifferent for rising and fallingTransitionsUse Worst Case – not Avg!
© Digital Integrated Circuits2nd
Sequential Circuits
Setup Time (MS register)Setup Time (MS register)
D
CLK
Q
Qm
D
Qm
Q
Setup = 0.21nSPassed D
Setup = 0.20nSFailed to pass D
© Digital Integrated Circuits2nd
Sequential Circuits
Cross-Coupled PairsCross-Coupled Pairs
NOR-based set-reset
S
R
Q
Q’
S0101
R0011
Q’Q’01-
QQ10-
© Digital Integrated Circuits2nd
Sequential Circuits
Cross-Coupled NANDCross-Coupled NAND
M1
M2
M3
M4Q
M5S
M6CLK
M7 R
M8 CLK
VDD
Q
Cross-coupled NANDsAdded clock
This is not used in datapaths any more,but is a basic register memory cell
© Digital Integrated Circuits2nd
Sequential Circuits
Sizing IssuesSizing Issues
Output voltage dependence on transistor width
Transient response
Q’ (
V)
W/L (M5,M6) M2=6
1
2
2.5 3.0 3.5 1 20
W=0.5
W=0.7
W=0.8
W=1
© Digital Integrated Circuits2nd
Sequential Circuits
Storage MechanismsStorage Mechanisms
D
CLK
CLK
Q
Dynamic (charge-based)
CLK
CLK
CLK
D
Q
Static
© Digital Integrated Circuits2nd
Sequential Circuits
Making a Dynamic Latch Pseudo-StaticMaking a Dynamic Latch Pseudo-Static
D
CLK
CLK
D
© Digital Integrated Circuits2nd
Sequential Circuits
Clk-Q Delay
TSetup-1
TClk-Q
Time
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Timet=0
ClockDataTSetup-1
© Digital Integrated Circuits2nd
Sequential Circuits
Clk-Q Delay
TSetup-1
TClk-Q
Time
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Timet=0
ClockDataTSetup-1
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
© Digital Integrated Circuits2nd
Sequential Circuits
Clk-Q Delay
TSetup-1
TClk-Q
Time
Timet=0
ClockDataTSetup-1
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
© Digital Integrated Circuits2nd
Sequential Circuits
Clk-Q Delay
TSetup-1
TClk-Q
Time
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Timet=0
ClockDataTSetup-1
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
© Digital Integrated Circuits2nd
Sequential Circuits
Timet=0
ClockDataTSetup-1
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
Clk-Q Delay
TSetup-1
TClk-Q
Time
© Digital Integrated Circuits2nd
Sequential Circuits
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Hold-1 case
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Timet=0
DataClockTHold-1
0
Clk-Q Delay
THold-1
TClk-Q
Time
© Digital Integrated Circuits2nd
Sequential Circuits
Clk-Q Delay
THold-1
TClk-Q
Time
Timet=0
DataClockTHold-1
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Hold-1 case
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
0
© Digital Integrated Circuits2nd
Sequential Circuits
Clk-Q Delay
THold-1
TClk-Q
Time
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Timet=0
DataClockTHold-1
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Hold-1 case
0
© Digital Integrated Circuits2nd
Sequential Circuits
Clk-Q Delay
THold-1
TClk-Q
Time
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Timet=0
Clock
THold-1
Data
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Hold-1 case
0
© Digital Integrated Circuits2nd
Sequential Circuits
Clk-Q Delay
THold-1
TClk-Q
Time
D
CN
QM
CP
D1SM
Inv1
Inv2TG1
Timet=0
Clock
THold-1
Data
Setup/Hold Time IllustrationsSetup/Hold Time Illustrations
Hold-1 case
0
© Digital Integrated Circuits2nd
Sequential Circuits
Other Latches/Registers: COther Latches/Registers: C22MOSMOS
M1
D Q
M3CLK
M4
M2
CLK
VDD
CL1
X
CL2
Master Stage
M5
M7CLK
CLK M8
M6
VDD
“Keepers” can be added to make circuit pseudo-static
© Digital Integrated Circuits2nd
Sequential Circuits
Insensitive to Clock-OverlapInsensitive to Clock-Overlap
M1
D Q
M4
M2
0 0
VDD
X
M5
M8
M6
VDD
(a) (0-0) overlap
M3
M1
D Q
M2
1
VDD
X
M71
M5
M6
VDD
(b) (1-1) overlap
© Digital Integrated Circuits2nd
Sequential Circuits
Other Latches/Registers: TSPCOther Latches/Registers: TSPC
Negative latch(transparent when CLK= 0)
Positive latch(transparent when CLK= 1)
© Digital Integrated Circuits2nd
Sequential Circuits
Pulse-Triggered LatchesPulse-Triggered LatchesAn Alternative ApproachAn Alternative Approach
Master-Slave Latches
D
Clk
Q D
Clk
Q
Clk
DataD
Clk
Q
Clk
Data
Pulse-Triggered Latch
L1 L2 L
Ways to design an edge-triggered sequential cell:
© Digital Integrated Circuits2nd
Sequential Circuits
Latch-Based PipelineLatch-Based Pipeline
CLK ~CLK CLK
F G
F G
© Digital Integrated Circuits2nd
Sequential Circuits
Non-Bistable Sequential Circuits─Non-Bistable Sequential Circuits─Schmitt TriggerSchmitt Trigger
In Out
Vin
Vout VOH
VOL
VM– VM+
•VTC with hysteresis
•Restores signal slopes
© Digital Integrated Circuits2nd
Sequential Circuits
Noise Suppression: Schmitt TriggerNoise Suppression: Schmitt Trigger
© Digital Integrated Circuits2nd
Sequential Circuits
CMOS Schmitt TriggerCMOS Schmitt Trigger
Moves switching thresholdof the first inverter
Vin
M2
M1
VDD
X Vout
M4
M3
© Digital Integrated Circuits2nd
Sequential Circuits
Schmitt Trigger Simulated VTCSchmitt Trigger Simulated VTC
2.5
VM2
VM1
Vin (V)
Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of thePMOS device M4 . The width isk* 0.5 m.m
2.0
1.5
1.0
0.5
0.00.0 0.5 1.0 1.5 2.0 2.5
2.5
k = 2k = 3
k = 4
k = 1
Vin (V)
2.0
1.5
1.0
0.5
0.00.0 0.5 1.0 1.5 2.0 2.5
© Digital Integrated Circuits2nd
Sequential Circuits
CMOS Schmitt Trigger (2)CMOS Schmitt Trigger (2)
VDD
VDD
OutIn
M1
M5
M2
X
M3
M4
M6
© Digital Integrated Circuits2nd
Sequential Circuits
Multivibrator CircuitsMultivibrator Circuits
Bistable Multivibrator
Monostable Multivibrator
Astable Multivibrator
flip-flop, Schmitt Trigger
one-shot
oscillator
S
R
T
© Digital Integrated Circuits2nd
Sequential Circuits
Transition-Triggered MonostableTransition-Triggered Monostable
DELAY
td
In
Outtd
© Digital Integrated Circuits2nd
Sequential Circuits
Monostable Trigger (RC-based)Monostable Trigger (RC-based)VDD
InOutA B
C
R
In
B
Outt
VM
t2t1
(a) Trigger circuit.
(b) Waveforms.
© Digital Integrated Circuits2nd
Sequential Circuits
Astable Multivibrators (Oscillators)Astable Multivibrators (Oscillators)
0 1 2 N-1
Ring Oscillator
simulated response of 5-stage oscillator
© Digital Integrated Circuits2nd
Sequential Circuits
Relaxation OscillatorRelaxation Oscillator
Out2
CR
Out1
Int
I1 I2
T = 2 (log3) RC
© Digital Integrated Circuits2nd
Sequential Circuits
Voltage Controller Oscillator (VCO)Voltage Controller Oscillator (VCO)
In
VDD
M3
M1
M2
M4
M5
VDD
M6
Vcontr Current starved inverter
Iref Iref
Schmitt Triggerrestores signal slopes
0.5 1.5 2.5Vcontr (V)
0.0
2
4
6
t pHL (
nsec
)
propagation delay as a functionof control voltage
© Digital Integrated Circuits2nd
Sequential Circuits
Differential Delay Element and VCODifferential Delay Element and VCO
in2
two stage VCO
v1
v2
v3
v4
Vctrl
Vo2 Vo1
in1
delay cell
simulated waveforms of 2-stage VCO
0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
20.51.5
V1 V2 V3 V4
time (ns)2.5 3.5
© Digital Integrated Circuits2nd
Sequential Circuits
Homework 7Homework 71. A common way to characterize registers is to measure the
timing aperture which is the total window in which transitions on data are not correctly output. This is done by making two clocks which are close, but not the same so that the relative phase drifts slowly with each cycle. Construct a pseudo-static master/slave flip-flop in SUE with the assumption that the input is driven by a unit inverter (2/1, min width nmos), the clock is driven by a 2x inverter. Optimize your designs to minimize the timing aperture (setup+hold) and clock to Q assuming the output load is 2 min inverters. Simulate your designs in SPICE and turn in both the designs (annotated schematics and spice results – plz. don’t waste paper!)
2. Do problem 1 again, with TSPC based flipflop. (High performance)