Design of Digital-to-Analog Converter

Qin ChenYong Wang

Dept. of Electrical EngineeringMar. 14th, 2006

EE597G Presentation:

Outline

• CMOS switch design and simulation

• Challenge and Solution

• R-2R Voltage DAC

• Schematic design and simulation results Chip Specifications

• Project Progress

CMOS Switch Circuit

Turn on resistance

Control signal is high:• When Vin<Vdd-Vgs1,

M1 is turned on;• When Vgs2<Vin<Vdd,

M2 is turned on;• The total parallel resis

tance make the turn-on resistance always low at the whole voltage range.

Simulation ResultsVG=0V, RL=10k Ohm

VG=+5V, RL=10k Ohm

Challenge

• For R-2R current DAC, how to change virtual ground to 2.5V in CMOS circuits?

• How to get rid of glitches?• How to implement large resistors (>10k ohm) in

layout? [next step]

Glitches in DAC output voltages

• Switches in DAC operate at different speeds output gli⇒tches occur when several input bits change together:

0111->1000

• Glitches are very noticeable on a video display:

Voltage-Mode R-2R Network DAC

Advantages and Disadvantages of Voltage R-2R DAC

Advantages:

• the constant output impedance, which eases the stabilization of any amplifier connected to the output node.

• No glitch, switch the arms of the ladder between low impedances, capacitive glitch currents tend not to flow in the load.

Disadvantages:

• operate over a wide voltage range (VREF to GND). This is difficult from a design and manufacturing viewpoint

• gain of the DAC cannot be adjusted by means of a resistor in series with the VREF terminal.

D9-D0: 10,0000,0000Vref: +5V

Linear output characterization

Testing the op amp

Freq. Response of Gain & Phase

Compensation

Compensation result

Output buffer

The output curve of output buffer

Voltage Reference

Characteristics of voltage reference

Rload(Ω) 5K

(I)

10K

(I/2)

40K

(I/8)

160K

(I/32)

5M

(I/1024)

Open

Vout (V) 2.5048 2.5027 2.5013 2.5008 2.5008 2.5008

5V

+

─

Vout=2.5V

5V

20K

20K

Rload

Building the DAC

Test the DAC

Test result of DAC

0 200 400 600 800 1000 1200

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6A

nal

og

ou

tpu

t (V

)

Digital input

What have been done

• OP Amp design and simulation

• CMOS switch design and simulation

• Schematic adjustment

• Schematic circuit design and simulation

Project Progress =>>

Week 1 Systematic design of chip

Week 2 Systematic design of chip (cont.)

Week 3 Circuit design

Week 4 Circuit design (cont.)

Week 5 Layout design

Week 6 Layout design (cont.)

Week 7 Final adjustments and verification

Week 8 Final adjustments and verification (cont.)