Ch4_ICprocess.ppt

Chapter 4Chapter 4

CMOS Process TechnologyCMOS Process Technology

Boonchuay SupmonchaiIntegrated Design Application Research (IDAR) Laboratory

July 5th, 2004; Revised - June 26th, 2006

B.SupmonchaiB.Supmonchai

2102-545 Digital ICs2102-545 Digital ICs CMOS Process Technology 2

OutlinesOutlines Chip-Making Process

Photolithography

CMOS IC Fabrication Processes Simple Process

Modern Process

Packaging Technology

Chip-Making Process: An OverviewChip-Making Process: An Overview

Crystal GrowthCrystal Growth PackagingPackaging

PhotolithographyPhotolithography

Growing the Silicon IngotGrowing the Silicon Ingot

From Smithsonian, 2000

Most common technique is the Czochralski (CZ) Czochralski (CZ) method developed by Mitsubishi Materials Silicon in the 50’s Length: up to 2 m

Diameter: 200 mm (8”) to 300 mm (12”)

Weight: Over 225 kg.

Pulling takes up to hundred hours

Czochralski (CZ) MethodCzochralski (CZ) Method

Crystal orientation is determined by seed orientationCrystal orientation is determined by seed orientation

Ingot diameter is determined by Ingot diameter is determined by temperaturetemperature, , orientationorientation, , and and extraction speedextraction speed..

Develop by Mitsubishi in the 50’s

1420 C1420 C

Wafer ShapingWafer Shaping

Ingot is cut around and ground down Ingot is cut around and ground down into a uniform diameter (8”-12”), then into a uniform diameter (8”-12”), then sliced into wafers of about 1 mm thick.sliced into wafers of about 1 mm thick.

QuickTime™ and a TIFF (Uncompressed) decompressor are needed to see th is p icture. Wire Saw MachineWire Saw Machine

The sliced wafers are mechanically The sliced wafers are mechanically lapped by the use of alumina abrasive lapped by the use of alumina abrasive material to remove surface roughness material to remove surface roughness and damages caused by the saw cut and damages caused by the saw cut and to improve the flatness of the wafer.and to improve the flatness of the wafer.

QuickTime™ and a TIFF (Uncompressed) decompressor are needed to see th is p icture.

Lapping MachineLapping Machine

Wafer Shaping (2)Wafer Shaping (2)

Mechanical damages induced during Mechanical damages induced during the previous processes are removed the previous processes are removed by chemical etching.by chemical etching.

The mechano-chemical polishing The mechano-chemical polishing process improves the flatness of the process improves the flatness of the wafer, making highly flat surface by wafer, making highly flat surface by the use of colloidal silica.the use of colloidal silica.

QuickTime™ and a TIFF (Uncompressed) decompressor are needed to see th is p icture. Wafer PolishersWafer Polishers

The Target: CMOS InverterThe Target: CMOS Inverter

PolysiliconPolysilicon

InIn OutOut

VVDDDD

GNDGND

PMOSPMOS 2

Metal 1Metal 1

NMOSNMOS

ContactsContacts

N WellN Well

LayoutLayout

OutOutInIn

VVDDDD

PMOSPMOS

NMOSNMOS

SchemeticSchemetic

Current CMOS StructureCurrent CMOS Structure

Define active areasEtch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers

CMOS Process at a GlanceCMOS Process at a Glance

One full photolithographyphotolithography sequence per layer (mask)

Built (roughly) from the bottom up

5 5 metal 2metal 2

4 4 metal 1metal 1

2 2 polysiliconpolysilicon

3 3 source and drain diffusionssource and drain diffusions

11 tubs (aka wells, active areas)tubs (aka wells, active areas)

Planarization: Polishing the WafersPlanarization: Polishing the Wafers

From Smithsonian, 2000

CMP (Chemical-Mechanical Planarization)CMP (Chemical-Mechanical Planarization) - Essential to keep the - Essential to keep the surface of the wafer approximately flat between processing surface of the wafer approximately flat between processing steps.steps.

liquid carrier with a liquid carrier with a suspended abrasive suspended abrasive component such as component such as aluminum oxide or aluminum oxide or silicasilica

Photolithography Photolithography

Modern Process

PhotolithographyPhotolithography An IC consists of

several layers of material that are manufactured in successive steps.

PhotolithographyPhotolithography is used to selectively process the layers, where the 2-D mask geometry is copied on the surface.

PhotoPhoto + + LithoLitho + + GraphyGraphy (Light) (Stone) (Writing)(Light) (Stone) (Writing)

== “Writing Stone with Light”“Writing Stone with Light”

oxide growthoxide growthoptical optical

maskmask

photoresist coatingphotoresist coatingphotoresist photoresist removal removal (ashing)(ashing)

spin, rinse, dryspin, rinse, dry acid etchacid etch

photoresist photoresist development development

stepper stepper exposureexposure

Photolithographic ProcessPhotolithographic Process

Ion implantationPlasma etching

Metal deposition

Typical operations in a single Typical operations in a single photolithographic processphotolithographic process

process process stepstep

Oxide Growth/Oxide DepositionOxide Growth/Oxide Deposition Oxidation of the silicon

surface creates a SiO2 layer that acts as an insulator.

Oxide layers are also used to isolate metal interconnections.

An annealing step is required to An annealing step is required to restore the crystal structure after restore the crystal structure after thermal oxidation.thermal oxidation.

Photoresist Deposition/CoatingPhotoresist Deposition/Coating The surface of the

wafer is coated with a photosensitive material, the photoresistphotoresist.

The mask pattern is developed on the photoresist, with UV light exposure.

Depending on the type of the photoresist (negativenegative or positivepositive), the exposed or unexposed parts of the photoresist change their property and become resistant to certain types of solvents.

Stepper ExposureStepper Exposure

The mask pattern is developed on the photoresist, with UV light exposureUV light exposure.

Glass Mask (reticle) containing the patterns to be transferred is brought in close proximity to the wafer

A Mask SampleA Mask Sample

Photoresist DevolopmentPhotoresist Devolopment The wafers are developed in either an acid or

base solution to remove the nonexposed (exposed) areas of the photoresist.

Once the exposed photoresist is removed, the wafer is “soft baked” at a low temperature to harden the photoresist.

Acid EtchingAcid Etching Etching is a common process to

pattern material on the surface.

Once the desired shape is patterned with photoresist, the unprotected areas are etched away.

Spin, Rinse, and DrySpin, Rinse, and Dry A special tool called SRD is used to clean the

wafers after each acid etch step

Use de-ionized water to remove any residue chemical substance.

Use nitrogen because it has no reaction with the silicon.

Various Process StepsVarious Process Steps The exposed area can now be subjected to a wide range

of process steps Ion implantation

Plasma (Dry) etching

Metal (Thin Film) deposition

Ashing - Photoresist RemovalAshing - Photoresist Removal A high-temperature plasma is used to selectively

remove the remaining photoresist without damaging previous layers.

After ashing the wafer is ready for the next round of photolithography.

Photolithographic Process ExamplePhotolithographic Process Example

Si-substrate

Silicon base material

1. After oxidation1. After oxidation

SiOSiO22

Si-substrate

2. After deposition of 2. After deposition of negative photoresistnegative photoresist

PhotoresistPhotoresistSiOSiO22

Si-substrate

3. Stepper exposure3. Stepper exposure

UV-light

Patternedoptical mask

Exposed resist

4. Photoresist Devolop and Bake4. Photoresist Devolop and Bake

Si-substrate

Exposed resist

heatheat

Photolithographic Process ExamplePhotolithographic Process Example

Si-substrate

8. Final result after 8. Final result after removal of resist removal of resist (ashing)(ashing)

6. After etching and spin, rinse and dry.6. After etching and spin, rinse and dry.

Si-substrate

Hardened resist

5. After development and 5. After development and etching of resist, chemical or etching of resist, chemical or plasma etch of SiOplasma etch of SiO22

Si-substrate

Hardened resist

Chemical or plasmaetch

• Step 7 is optional in this Step 7 is optional in this example. The step is need example. The step is need only in implanting a well or only in implanting a well or doping polysilicon doping polysilicon

• Planarization step is applied Planarization step is applied at least once in a cycle of at least once in a cycle of photolithography photolithography

1000 C1000 C

DiffusionDiffusion:: Wafer is exposed to Wafer is exposed to gas containing dopant under gas containing dopant under high temperature (900-1100 C)high temperature (900-1100 C)

Ion ImplantationIon Implantation:: A beam of A beam of dopant ions is swept over the dopant ions is swept over the surface - causing damage to surface - causing damage to substrate, need annealingsubstrate, need annealing

Purified Purified Ion beamIon beam

Diffusion and Ion ImplantationDiffusion and Ion Implantation Change the electrical characteristics of silicon locally by adding

doping agents to the exposed area.

The dopant ions penetrate the surface with a penetration depth that is proportional to their kinetic energy.

Photolithography

CMOS IC Fabrication ProcessesCMOS IC Fabrication Processes Simple ProcessSimple Process

Modern Process

Photolithography MasksPhotolithography Masks Each photolithography step during fabrication

must be defined by a separate photolithography mask.

Each mask layer must be drawn (either manually or using a design automation tool) according to the layout design ruleslayout design rules.

The combination (superposition) of all necessary mask layers completely defines the circuit to be fabricated.

Layout Design RulesLayout Design Rules To allow reliable fabrication of each structure,

the mask layers must conform to a set of geometric layout design rules.

Usually, the rules (for example: minimum distance and/or separation between layers) are expressed as multiples of a scaling factor - lambda (lambda ()) - minimum resolution of a technology

For each different fabrication technology, lambda factor can be different.

Examples of Layout Design RulesExamples of Layout Design Rules

A Minimum-Sized TransistorA Minimum-Sized Transistor

More Example of Layout RulesMore Example of Layout Rules

Self-Aligned ProcessSelf-Aligned Process

1. Create thin oxide in the 1. Create thin oxide in the ““activeactive” regions, thick ” regions, thick elsewhereelsewhere

4. 4. Implant dopantImplant dopant (see previous slides(see previous slides))

3. Etch thin oxide from active 3. Etch thin oxide from active region (poly acts as a mask region (poly acts as a mask for the diffusion)for the diffusion)

2. Deposit 2. Deposit polysiliconpolysilicon

Notes on Self-Aligned ProcessNotes on Self-Aligned Process Polysilicon gate is patterned beforebefore source and

drain are created, Thereby defining the precise location of the channel

region and the locations of the source and drain regions relative to the gate.

And consequently reducing parasitic capacitances in the transistor.

However, this technique cannot completely stop lateral diffusion Accounts for difference between drawn transistor difference between drawn transistor

dimensions and actual onesdimensions and actual ones..

Simplified CMOS Inverter ProcessSimplified CMOS Inverter Process

cut line

p well

P-Well MaskP-Well Mask

Active MaskActive Mask

Poly MaskPoly Mask

P+ Select (Source/Drain) MaskP+ Select (Source/Drain) Mask

Self-Aligned GateSelf-Aligned Gate

N+ Select (Source/Drain) MaskN+ Select (Source/Drain) Mask

Self-Aligned GateSelf-Aligned Gate

Contact MaskContact Mask

Metal MaskMetal Mask

Photolithography

CMOS IC Fabrication ProcessesCMOS IC Fabrication Processes Simple Process

Modern ProcessModern Process

A Modern CMOS ProcessA Modern CMOS Process

Both n- and p- wells grown on top of an epitaxial layer Both n- and p- wells grown on top of an epitaxial layer (using trench isolation areas of SiO(using trench isolation areas of SiO22))

Dual-Well Trench-Isolated CMOSDual-Well Trench-Isolated CMOS

p well n well

gate oxide

Al (Cu)

tungsten

field oxide

TrenchTrench

Modern CMOS Process Walk-ThroughModern CMOS Process Walk-Through

After plasma etch of insulating trenches using the inverse of the active area mask

After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer)p+

p-epiSiO2

Base material: p+p+ substrate with p-epip-epi layer

Modern CMOS Process Walk-Through Modern CMOS Process Walk-Through (2)(2)

SiO2After trench filling, CMP planarization, and removal of sacrificial nitride

After n-well and VTp adjust implants

After p-well and VTn adjust implants

After polysilicon deposition and etch

poly(silicon)

After n+ source/drain and p+ source/drain implants. These steps also dope the polysilicon.

After deposition of SiO2 insulator and contact hole etch

After deposition and patterning of first Al layer.

After deposition of SiO2 insulator, etching of via’s, deposition and patterning of second layer of Al.

State-of-the-Art ExampleState-of-the-Art Example

Interconnect Delay CrisisInterconnect Delay Crisis As technology shrinks, interconnect delay has

more and more impact on the overall design performance. Wire delay now accounts for > 40% of total delay in a

circuit

There are 2 key points where interconnect delay can be reduced. Use low-resistivity materialUse low-resistivity material

Copper in stead of Aluminum (what is the best conductor?)

Use insulator material with a lower dielectric Use insulator material with a lower dielectric constant (k) than SiOconstant (k) than SiO2 2 (Reduce coupling)

Advanced MetallizationAdvanced Metallization

Silicon-on-Insulator (SOI)Silicon-on-Insulator (SOI) The idea is to construct the transistor structures in a very thin layer

of silicon on an insulatinginsulating material rather than a common substrate as in bulk CMOS process.

This reduces parasitic capacitances and eliminates substrate noise coupling.

Insulator (SiOInsulator (SiO22))

TransistorTransistor

SOI ExampleSOI Example

22% improvement in performance22% improvement in performance

Fabrication Cost - Moore’s LawFabrication Cost - Moore’s Law

Initial investment of new facilities is too expensive!Initial investment of new facilities is too expensive!

Photolithography

Modern Process

Packaging TechnologyPackaging Technology

Packaging TechnologyPackaging Technology Many high-performance chips failed stringent

test specifications after packaging because the designer (usually novice!) have not included various effects of packaging constraints and parasitics into their designs. Ground planes, power planes, and bonding pads

greatly affect the behavior of on-chip power and ground bus.

Length of bonding wire and lead length in a package generate a voltage drop in the output circuit.

Inappropriate type of package body can cause thermal runaway and hence damage the ICs.

Packaging RequirementsPackaging Requirements ElectricalElectrical: Low parasitics

Low capacitance and Inductance

MechanicalMechanical: Reliable and robust Moisture-proof

High pin density

ThermalThermal: Efficient heat removal High thermal conductivity

Low thermal expansion coefficient

EconomicalEconomical: Cheap

Lead Frame

Substrate

Wire Bonding

Bonding TechniquesBonding TechniquesWire BondingWire Bonding

High and unpredictable value of parasiticsHigh and unpredictable value of parasitics

Tape-Automated Bonding (TAB)Tape-Automated Bonding (TAB)

(a) Polymer Tape with imprinted

(b) Die attachment using solder bumps.

wiring pattern.

Substrate

Solder BumpFilm + Pattern

Sprockethole

Polymer film

Leadframe

Testpads

Polymer Tape with imprinted Polymer Tape with imprinted Wiring patternWiring pattern

(a) Polymer Tape with imprinted

(b) Die attachment using solder bumps.

wiring pattern.

Substrate

Solder BumpFilm + Pattern

Sprockethole

Polymer film

Leadframe

Testpads

Die Attachment using Die Attachment using Soldier bumpsSoldier bumps

Highly Automated, Highly Automated, Eliminate long bonding Eliminate long bonding wireswires

Solder bumps

Substrate

Interconnect

layers

Flip-Chip BondingFlip-Chip Bonding

Alleviate power- and clock-distribution problemAlleviate power- and clock-distribution problem

Package-to-Board InterconnectPackage-to-Board Interconnect

(a) Through-Hole Mounting (b) Surface Mount

Through-Hole MountingThrough-Hole Mounting

(a) Through-Hole Mounting (b) Surface Mount

Surface MountingSurface Mounting

Sturdy, Sturdy, Mechanically reliably,Mechanically reliably,Lower packaging densityLower packaging density

Difficult to mount Difficult to mount Mechanical weaker structureMechanical weaker structureHigher packaging densityHigher packaging density

PGA - Pin Grid ArrayPGA - Pin Grid Array

DIP - Dual-In-Line PinDIP - Dual-In-Line Pin

QFP - Quad Flat PackQFP - Quad Flat Pack

Package TypesPackage Types

Package and Bonding ParametersPackage and Bonding Parameters

Multi-Chip ModulesMulti-Chip Modules Multiple chips are

assembled on a common substrate contained in a single package A large number of critical

interconnections between the chips can be made withinwithin the package.

AdvantagesAdvantages are savings of overall system size, reduced package lead counts, and faster operation.

Ch4_ICprocess.ppt

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Transcript of Ch4_ICprocess.ppt

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