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tions (3 /im and 5 /im) and three electrode widths (1 /im, 2 /im
and 3 fitn), the device areas were adjusted to obtain the target
capacitance values. A typical frequency response is depicted in
Fig.
2
I/V characteristic of MIL PIN device
Fig. 3. The 3 dB roll-off frequency n ear 8 G H z ap pears to be
limited by the carrier transit time rather than the electrode
capacitance. This observation is also consistent with the
anticipated roll-off frequency of our largest detectors. (With
220 fF capacitances and 50 Q load resistances, the theoretical,
RC
time-con stant-limited ba ndw idth is 14 GH z.) Althou gh it
is possible to attain even larger detector geometries without
affecting ou r observe d 3 dB roll-off po int, th e limited real
estate available on an IC chip tends to discourage the devel-
opment of extremely large detector areas
(> 200 ;im x 200/^m).
Fig. 3
Typical frequency response from 2 G Hz to 8 GHz
Lo g of am plitud e response is 5 dB/d iv and reference level is set at
—10 dB. 5 dB fluctuations app aren t in res ponse curve between
3 GH z and 7 GH z are believed present because packaging has not
been optimised
In summary, a detector design which can be implemented
on a substrate in common with other IC components allows
the fabrication of detector/amplifier ICs. We have demon-
strated than an interdigitated MIL PIN device meets this
requirement without sacrificing the desirable features of high
speed and large detection area.
D.
J. JACKSON
16th
December
1985
D. L. PERSECHINI
Hughes Research Laboratories
Malibu, CA 90265, USA
References
1 SLAYMAN, c. w., and FIGUEROA, L. :
IEEE Electron Device L ett.,
1981, EDL-2 p. 112; SUGETA, T., an d URISU, T.:
IEEE Transactions
Electron Devices,
ED-26 1979, 1855
2 FORREST, s. R.:
J. Lightwave Technol.,
1985, LT3 p. 347
3 DIADIUK, v., and GROVES, S. H.:
Appl. Phys. Lett.,
1985, 46, p. 157
NOVEL CMOS SCHMITT TRIGGER
Indexing terms: Semicondu ctor devices and materials, MOS
structures and devices
A novel CMOS Schmitt trigger circuit has been realised,
using only five MOS transistors. The circuit always guar-
antees hysteresis, even with very large process variations. The
switching speed of the new Schmitt trigger is higher, com-
pared to previously reported CMOS Schmitt triggers.
Introduction: The Sch mitt trigger is a circuit that converts a
varying voltage into a stable logical signal (one or zero). The
DC transfer characteristic needs hysteresis to reduce the sensi-
tivity to noise and disturbances. In many applications it is
necessary to control the hysteresis width from a few tens of
millivolts, up to volts. In the new Schmitt trigger circuit, this
hysteresis voltage is controlled by the dimension of only one
transistor. Even if the hysteresis voltage has been chosen very
small, the hysteresis is always guaranteed even under large
process variations.
The Schmitt trigger circuit: The integration of a CMOS
Schmitt trigger requires special circuits to cancel the resistors
commonly used in discrete Schmitt triggers.
1
In Fig. la a
commonly used CMOS Schmitt trigger is shown,
2
3
and in
Fig. \b the new CMOS Schmitt trigger. The new Schmitt
out
rfC
d d
int
M,M,
o ut
4
Fig. 1
a
Commonly used Schmitt trigger circuit
b
New Schmitt trigger circuit
trigger consists of two invertors (M
1 ;
M
2
and M
4
, M
5
) and an
extra feedback transistor (M
3
). It is this extra transistor that
always guarantees the hysteresis of the Schmitt trigger.
If V
in
= V
ss
,
in t
is high and
ou t
is low. It means that tran-
sistor M
3
is off. If V
in
increases, the first invertor (M,, M
2
) will
switch with a threshold voltage V
Oi
) defined by the transistors
M, and M
2
:
1 + m
(1)
with
l k
p
W/L)l\
where l^
n
, ^
p
are the threshold voltages and
k
n
, k
p
are the
transconductance parameters of the NMOS and PMOS t ran-
sistors, respectively. If the first inverter is switching, the second
inverter (M
4
, M
5
) will be switching as well. It means that M
3
ELECTRONICS LETTERS 13th February 1986 Vol. 22 No. 4
20 3
8/18/2019 1986 steyaert novel CMOS Schmitt trigger.pdf
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is switched on, and will generate positive feedback
V
int
decrease—>
ou t
increase—• M
3
is more on—• V
im
decreases
more—* ..
.)•
From this moment on the Schmitt trigger is in the
other state.
If v
in
= V
dd
,
in t
is low and
ou t
is high. It means that tran-
sistor M
3
is now switched on, and works as a current source.
To switch the first inverter the threshold voltage V
l0
has to be
lower than V
01
to compensate for this extra current sink from
transistor M
3
, or
k
p
= 15-2
v — v —
2(1 + m)
2)
with
n =
k
n
W/L)3\
UW QlJ
As soon as the input voltage is lower than V
l0
, again positive
feedback switches the Schmitt trigger to the other state.
The hysteresis voltage of this Schmitt trigger is given by the
second part of eqn. 2 and can be controlled by W/L) of tran-
sistor M
3
. As can be seen, there is always a hysteresis even
with large variations in dimensions {W/L ratio) or process
variations k
n
, k
p
,
tn
and
V
tp
).
If, for example, the parameter of
transistor M
3
k
n
W/L)3) is reduced by 50%, the hysteresis
width will be 30% reduced, but the hysteresis is still present
even if the hysteresis width is designed to be few tens of milli-
volts. In the previously reported CMOS Schmitt trigger, such
a large variation in one of the transistors M
l 5
M
3
, M
5
or M
6
would cause the hysteresis to disappear if this is designed to
be smaller than 500 mV.
The advantage of this new circuit, compared with pre-
viously reported Schmitt triggers, is the higher switching
speed. This switching speed is limited to the slew rate of the
internal node V
int
). The slew rate is defined by the current
available divided by the load capacitor (C
t
). In this circuit
C
l
is only the gate-source capacitor
C
gs
)
of the next inverter
(only two transistors) and the drain-bulk capacitor
C
db
),
which in this case is negligible. In the Schmitt trigger of
Fig.
la C
x
is given by four C
gs
values, whereby the extra two
transistors need to be very large for practical use, which
causes large values of C
gs
. It means that in the first order the
switching speed of the new circuit is more than two times
higher for the same current consumption.
CMOS realisation and measurements: The new circuit has been
designed in a 3 /zm CMOS process. The design specifications
for the threshold voltages were: K
01
= 2-5 V and
V
l0
= 2 V.
The transistor dimensions are given in Table
1.
The circuit has
Table 1
DIMENSIONS OF TRANSISTORS IN
DESIGNED NEW SCHMITT TRIGGER
W/L
M
t
M
2
M
3
M
4
M
5
5/7
5/18
5/40
5/7
5/18
been extensively simulated in SPICE level 2. In Fig. 2 the DC
transfer and the AC transfer curve of
in t
and
ou t
are given. As
can be seen, the threshold voltages are V
Ql
= 2-5 V and V
l0
=
21 V. The delay with a load of 200 fF is about 65 ns. In
Fig. 3 a microphotograph of the circuit is given. The Schmitt
trigger is used to realise a PDM- PPM convertor. In Fig. 4
measurement results of the integrated Schmitt trigger are
shown. The input signal is a triangular wave. Out of this
measurement, the threshold voltages were deduced to be
V
0l
= 2-48 V and V
l0
= 1-8 V (spread a = 50 mV). The differ-
ences between measurements and the simulations are mainly
found in the used threshold voltages. The results of a SPICE
simulation using the extracted transistor parameters and
threshold voltages of that run are: V
0l
= 2-56 V and V
l0
=
1-82 V V
tn
= 0-7 V, V
tp
= 0-78 V, k
n
= 40-7
p
/iA/V). The measured performance of the new Schmitt trigger
compares very well with the simulation.
Fig.
2
Simulated DC and AC transfer curve of Schmitt trigger
Fig.
3
Microphotograph of designed Schmitt trigger
Fig.
4
Measured transfer curve of designed Schmitt trigger
Conclusion: A new CMOS Schmitt trigger has been designed
and measured. The relations to calculate the threshold volt-
ages and the hysteresis width are described. The hysteresis of
this new Schmitt trigger is always guaranteed, even with very
large process variations. From the measurements, it is shown
that the new structure has a very excellent performance with a
very simple circuit.
M. STEYAERT*
W.
SANSEN
Katholieke Universiteit Leuven
Departement Elektrotechniek-Ajdeling
E.S.A.T.
Kardinaal Mercierlaan 94
B-3030
Heverlee, Belgium
Supported by the Belgium IWONL
6th December
1985
204
ELECTRONICS LETTERS
13th
February
1986 Vol. 22 No. 4
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eferen es
1 RIDDERS, 'Accurate determination of threshold voltage levels of a
Schmitt trigger',
IEEE Trans.,
1985,
CAS-32
2
BRANKO,
'Modified CMOS
invertors , Microelectron. J.,
1983, 14
3
NAGARAJ, SATYAM,
'Multistage monostable multivibrator using
load coupled regenerative feedback',
Electron. Lett.,
1981, 17, pp.
159 160
EFFICIENT
RQ TECHNIQUE USING SOFT
DEMODULATION
Indexing terms:
Codes,
Demodulation
In
the letter a new technique for increas ing the efficiency of
an automatic-repeat-request communication system is
described.
This technique uses all the received versions of a
codeword,
and also those versions containing
errors.
Such a
strategy, together with a soft demodulation of each received
symbol , is particularly efficient when applied to ARQ
schemes
in which each block erroneously received is
retransmitted
many
times.
Automatic-repeat-request (ARQ) techniques are widely used
to improve the reliability of communication systems using
many types of practical channel. 'Stop-and-wait', 'go-back-JV'
and 'selective ARQ' schemes are the best known methods.
1
'
2
Stop-and-wait and go-back-iV schemes present a lower imple-
mentation cost with respect to the selective scheme; on the
other hand, their efficiency falls rapidly with the increase in
the channel error probability.
Sastry
3
proposed a modification of the classical stop-and-
wait and go-back-N schemes to increase the throughput by
reducing the wasted time spent in the waiting or in the
retransmission state. Each new codeword
c
is first transmitted
only once, while it is repeated i times when a repeat request is
received. Recently, a continuous ARQ scheme has been pro-
posed by Moeneclaey and Bruneel,
4
in which each block is
always transmitted N times, where N is the number of blocks
which can be transmitted during the round-trip delay.
In this letter it is shown that the performance of the
previous ARQ schemes, in which the same codeword is
retransmitted many times, can be significantly improved by
introducing a soft decision demodulation.
5
A signal having amplitude d
m
A is used to transmit the
binary symbol d
m
d
m
— ±
1).
Each information-bearing
sequence of k symbols is encoded into a codeword c through a
code of type (n, k). The positive signal region (0 — A) is lin-
early quantised in n
L
levels; the quantisation step is d =
2A/ 2n
L
— 1); the upper level lies between A — d/2) and
+00.
Similarly, n
L
levels are defined for the negative signal region.
With the /th quantisation positive level, the integer / is associ-
ated, and with the /th negative level, the integer —/. We
denote by r
jt
m
t), for 1