11

Synchronization ofSynchronization ofcomplex systemscomplex systems

Jordi CortadellaJordi Cortadella

Universitat Politecnica de CatalunyaUniversitat Politecnica de Catalunya

Barcelona, SpainBarcelona, Spain

Thanks to A. Chakraborty, T. Chelcea,Thanks to A. Chakraborty, T. Chelcea,M. Greenstreet and S. NowickM. Greenstreet and S. Nowick

22

Multiple clock domainsMultiple clock domains

CLK

f1/f0

f2/f0

f3/f0

CLK(f0)

CLK

1C

LK2

CLK

3

CLK

0

Single clock(Mesochronous)

Rational clock frequenciesIndependent clocks

(plesiochronousif frequenciesclosely match)

33

The problem: metastabilityThe problem: metastability

D Q

ФT

D Q

?

D

Q

ФRФR setup hold

44

Classical “synchronous” solutionClassical “synchronous” solution

Wffe

D

rtMTBF

2

D Q D Q D Q D Q

ФT ФR

Mean Time Between Failures fФ: frequency of the clock fD: frequency of the data tr: resolve time available W: metastability window : resolve time constant

# FFs# FFs MTBFMTBF

1 FF1 FF 15 min15 min

2 FF2 FF 9 days9 days

3 FF3 FF 23 years23 years

Example

55

How to live with metastability ?How to live with metastability ?

Metastability cannot be avoided, it must be tolerated.Metastability cannot be avoided, it must be tolerated.

Having a decent MTBF (Having a decent MTBF ( years) may result in a years) may result in atangible impact in latencytangible impact in latency

Purely asynchronous systems can be designedPurely asynchronous systems can be designedfailure-freefailure-free

Synchronous and mixed synchronous-asynchronous Synchronous and mixed synchronous-asynchronous systems need mechanisms with impact in latencysystems need mechanisms with impact in latency

But latency can be hidden in many cases …But latency can be hidden in many cases …

66

Different approachesDifferent approaches

Pausible Clocks (Yun & Donohue 1996)Pausible Clocks (Yun & Donohue 1996)

Predict metastability-free transmission windows for domains with Predict metastability-free transmission windows for domains with related clocks (Chakraborty & Greenstreet 2003)related clocks (Chakraborty & Greenstreet 2003)

Use the waiting time in FIFOs to resolve metastabilityUse the waiting time in FIFOs to resolve metastability(Chelcea & Nowick 2001)(Chelcea & Nowick 2001)

And others …And others …

The term “Globally Asynchronous, Locally Synchronous” is typically The term “Globally Asynchronous, Locally Synchronous” is typically used for these systems (Chapiro 1984)used for these systems (Chapiro 1984)

77

Mutual exclusion elementMutual exclusion element

req1

req2

ack1

ack2

0

0

1

1

0

0

88

Metastability

99

Mutual exclusion elementMutual exclusion element

req1

req2

ack2

ack1

0

0

1

1

0

0

An asynchronous data latch with MS resolver can be built similarly

Metastability resolver

1010

Abstraction of the MUTEXAbstraction of the MUTEX

R1

R2

G1

G2

MUTEX

1111

A pausible clock generatorA pausible clock generator

delay

[δ1, δ2]

Environment

MUTEX

1212

Pausible clocksPausible clocks

delay

[δ1, δ2]

ME

CLK

Cntr

MUTEXFF

Req

Ack

Yun & Dooply, IEEE Trans. VLSI, Dec. 1999Moore et al., ASYNC 2002

1313

STARI (STARI (SSelf-elf-TTimed imed AAt t RReceiver’s eceiver’s IInput)nput)

Both clocks are generated from the same sourceBoth clocks are generated from the same sourceThe FIFO compensates for skew between The FIFO compensates for skew between transmitter and receivertransmitter and receiverM. Greenstreet, 1993M. Greenstreet, 1993

1414

A Minimalist InterfaceA Minimalist Interface

FIFO reduces to latch-X and a latch controllerFIFO reduces to latch-X and a latch controller

ΦΦxx can always be generated in such a way as to can always be generated in such a way as to

reliably transfer data from input to outputreliably transfer data from input to output

Chakraborty & Greenstreet, 2002Chakraborty & Greenstreet, 2002

1515

A Minimalist Interface: 3 scenariosA Minimalist Interface: 3 scenarios

Latch-X setup & hold

Latch-R setup & hold

Фx Permitted

The scenario is chosenat initialization

1616

A Minimalist Interface: latch controllerA Minimalist Interface: latch controller

The controller detects which transition arrives first (from ΦT and ΦR)and generates ΦX accordingly

1717

A Minimalist Interface: rational clocksA Minimalist Interface: rational clocks

1818

A Minimalist Interface: arbitrary clocksA Minimalist Interface: arbitrary clocks

Assumption: clocks are stableAssumption: clocks are stable

Each domain estimates the other’s frequencyEach domain estimates the other’s frequency

Residual error corrected using stuff bitsResidual error corrected using stuff bits

1919

Mixed-Timing InterfacesMixed-Timing Interfaces

AsynchronousDomain

SynchronousDomain 1

SynchronousDomain 2

Async-Sync FIFO

Asyn

c-S

yn

c F

IFO

Syn

c-A

syn

c F

IFO

Mixed-Clock FIFO’s

Chelcea & Nowick, 2001Chelcea & Nowick, 2001

2020

Mixed-Clock FIFO: Block LevelMixed-Clock FIFO: Block Level

full

req_put

data_put

CLK_put

req_get

valid_get

empty

data_get

CLK_getMix

ed

-Clo

ck

FIF

Osynchronous synchronous putput inteface inteface

synchronous synchronous getget interface interface

2121

Mixed-Clock FIFO: Block LevelMixed-Clock FIFO: Block Level

full

req_put

data_put

CLK_put

req_get

valid_get

empty

data_get

CLK_getMix

ed

-Clo

ck

FIF

O

Bus for data items

Controls get operations

Initiates get operations

Bus for data items

synchronous synchronous putput inteface inteface

synchronous synchronous getget interface interface

Initiates put operations

Controls put operations

2222

full

req_put

data_put

CLK_put

req_get

valid_get

empty

data_get

CLK_getMix

ed

-Clo

ck

FIF

Osynchronous synchronous putput inteface inteface

synchronous synchronous getget interface interface

Indicates when FIFO empty

Indicates when FIFO fullIndicates data items validity

(always 1 in this design)

Mixed-Clock FIFO: Block LevelMixed-Clock FIFO: Block Level

2323

Mixed-Clock FIFO: ArchitectureMixed-Clock FIFO: Architecture

cell cell cell cell cell

Ge

tC

on

tro

ller

Empty Detector

Full DetectorPut

Controller

full

req_put

data_put

CLK_put

CLK_getdata_get

req_get

valid_get

empty

2424

REG

Mixed-Clock FIFO: Cell ImplementationMixed-Clock FIFO: Cell Implementation

En

En

f_ie_i

ptok_out ptok_in

gtok_ingtok_out

CLK_get en_get valid data_get

CLK_put en_put req_putdata_put

SR

2525

REG

Mixed-Clock FIFO: Cell ImplementationMixed-Clock FIFO: Cell Implementation

En

En

f_ie_i

ptok_out ptok_in

gtok_ingtok_out

CLK_get data_get

CLK_put en_put data_put

SR

GET INTERFACEGET INTERFACE

PUT INTERFACEPUT INTERFACE

en_get valid

req_put

2626

Synchronization: summarySynchronization: summary

Resolving metastability implies latencyResolving metastability implies latency

Latency can be often hidden (FIFOs, Chelcea & Nowick)Latency can be often hidden (FIFOs, Chelcea & Nowick)

Clock frequencies can be estimated and clock edges Clock frequencies can be estimated and clock edges predicted under the assumption of stable clocks predicted under the assumption of stable clocks (Chakraborty & Greenstreet)(Chakraborty & Greenstreet)

Pausible clocks are also possible (Yun & Donohue 1996)Pausible clocks are also possible (Yun & Donohue 1996)

But still the nicest solutions are totally asynchronousBut still the nicest solutions are totally asynchronous As presented by Fulcrum Microsystems in the last lectureAs presented by Fulcrum Microsystems in the last lecture