Post on 17-Jan-2016
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CHAP3: MOS Field-EffectTransistors (MOSFETs)
Similarities:• Amplifiers• Switching devices• Impedance matching circuitsDifferences:• FETs are voltage controlled devices. BJTs are current controlleddevices.• FETs have a higher input impedance. BJTs have higher gains.• FETs are less sensitive to temperature variations and are more easily integrated on ICs.• FETs are generally more static sensitive than BJTs.
FETs vs. BJTs
FET Types•JFET: Junction FET•MOSFET: Metal–Oxide–Semiconductor FET
D-MOSFET: Depletion MOSFETE-MOSFET: Enhancement MOSFET
FET Operating CharacteristicsJFET operation can be compared to a water spigot.
The source of water pressure is the accumulation of electrons at the negative pole of the drain-source voltage.The drain of water is the electron deficiency (or holes) at the positive pole of the applied voltage.The control of flow of water is the gate voltage that controls the width of the n-channel and, therefore, the flow of charges from source todrain.
FET Operation: The Basic IdeaThere are three basic operating conditions for a JFET:
• VGS = 0, VDS increasing to some positive value• VGS < 0, VDS at some positive value• Voltage-controlled resistor
FET ( Field Effect Transistor)
1. Unipolar device i. e. operation depends on only one type of charge carriers (h or e)
2. Voltage controlled Device (gate voltage controls drain current)
3. Very high input impedance (109-1012 )4. Source and drain are interchangeable in most Low-frequency
applications
5. Low Voltage Low Current Operation is possible (Low-power consumption)
6. Less Noisy as Compared to BJT7. No minority carrier storage (Turn off is faster) 8. Self limiting device9. Very small in size, occupies very small space in ICs10. Low voltage low current operation is possible in MOSFETS 11. Zero temperature drift of out put is possible
Few important advantages of FET over conventional Transistors
Types of Field Effect Transistors (The Classification)
» JFET
MOSFET (IGFET)
n-Channel JFET
p-Channel JFET
n-Channel EMOSFET
p-Channel EMOSFET
Enhancement MOSFET
Depletion MOSFET
n-Channel DMOSFET
p-Channel DMOSFET
FET
6
Figure Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.
Fundamentals of FET
7
Figure The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.
8
Figure An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS. Note that the depletion region is not shown (for simplicity).
9
Figure The iD–vDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS, is kept small. The device operates as a linear
resistor whose value is controlled by vGS.
10
Figure Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt.
11
Figure The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.
12
Figure: Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS – Vt’ the channel is pinched off at the drain end. Increasing vDS above vGS – Vt
has little effect (theoretically, no effect) on the channel’s shape.
Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics.
Non-saturation (Ohmic) Region:
The drain current is given by
2'
2
1DSDStGSDS VVVV
L
WkI
2
21
221
'
'
tGS
DSDS
VVL
WK
VL
WKI
2
1 and
P
GSDSSDS V
VII
Where, IDSS is the short circuit drain current, VP is the pinch off voltage
Output or Drain (VD-ID) Characteristics of n-MOSFET
Saturation (or Pinchoff) Region:
tGSDS VVV
tGSDS VVV
Application1:
15
Application2:
16
Figure: (a) Circuit for Example. (b) The circuit with some of the analysis details shown.
Application3:
Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics.
Non-saturation (Ohmic) Region:
The drain current is given by
2
2 2
2DS
DSPGSP
DSSDS
VVVV
V
II
2
2 PGSP
DSSDS
VVV
II
2
1 and
P
GSDSSDS V
VII
Where, IDSS is the short circuit drain current, VP is the pinch off voltage
Output or Drain (VD-ID) Characteristics of n-JFET
Saturation (or Pinchoff) Region:
PGSDSVVV
PGSDSVVV
Figure: Typical drain characteristics of an n-channel JFET.
VD-ID Characteristics of EMOS FET
Saturation or Pinch off Reg.
Locus of pts where PGSDS VVV
Figure: Transfer (or Mutual) Characteristics of n-Channel JFET
2
1
P
GSDSSDS V
VII
IDSS
VGS (off)=VP
Transfer (Mutual) Characteristics of n-Channel JFET
JFET Transfer CurveThis graph shows the value of ID for a given value
of VGS
Figure: Transfer (or Mutual) Characteristics of n-Channel FET
2
1
P
GSDSSDS V
VII
IDSS
VGS (off)=VP
Transfer (Mutual) Characteristics of n-Channel FET
Biasing Circuits used for JFET
Just as we learned that the BJT must be biased for proper
operation, the JFET also must be biased for operation point
(ID, VGS, VDS)
In most cases the ideal Q-point will be at the middle of the
transfer characteristic curve, which is about half of the IDSS.
3 types of DC JFET biasing configurations
Fixed bias circuit
Self bias circuit
Potential Divider bias circuit
Fixed-bias
VDS
+_
VGG
VGS_
RD
VDD
RG
+C1
C2
Fixed-bias
+
Vin
_
+
Vout
_
+ • Use two voltage sources: VGG, VDD
• VGG is reverse-biased at the Gate – Source (G-S) terminal, thus no current flows through RG (IG = 0).
Fixed-bias..• DC analysis
– All capacitors replaced with open-circuit
VDS
+_
VGG
VGS_
RD
VDD
RG
+
Loop 1
Fixed-bias…
1. Input Loop • By using KVL at loop 1:
VGG + VGS = 0 VGS = - VGG
• Replace VGS = -VGG in Shockley’s Eq. ,therefore:
2. Output loop- VDD + IDRD + VDS = 0
VDS = VDD – IDRD
3. Then, plot graph by using Shockley’s Eq
2
)(
2
)(
11
offGS
GGDSS
offGS
GSDSSD V
VI
V
VII
Example : Fixed-bias
2GS
D DSSP
V I = I 1 -
V
Determine the following network:
1. VGSQ
2. IDQ
3. VD
4. VG
5. VS
Solutions
GSQ GGV = - V = - 2
2 2GS
DQ DSSP
2
V - 2 I = I 1 - = 10mA 1 -
V -8
= 10mA 0 5.6.75 25mA
DS DD D DV = V - I R = 16 - 5.625mA 2k
= 16V -11.25V = 4.75V
D D S
G G S
S
V = V - V =
V = V
4.75V
-- V =
V
2V
= 0V
Graphical solution for the network
GSQ GGV = - V = - 2
DQ 5.I = 625mA
DS 4V = .75V
D
G
S
V =
V =
4.75V
- 2V
V = 0V
Self-bias
• Using only one voltage source
DC analysis of the self-bias configuration.
RS D S
GS RS
GS RS
D S
V = I R
-V - V = 0
V = -V
= - I R
G G GRG
RG
Since I 0A, V I R
thus V 0A,
Q point for VGS
VGS + VRS = 0
Defining a point on the self-bias line.
Vgs ID0 IDSS
0.3Vp IDSS/2
0.5Vp IDSS/4
Vp 0 mA
Sketching the self-bias line.
D DSS
GS D S
DSS S
I = I 2
V = -I R
I R = -
2 DS DD D S DV = V - I R + R
S D SV = I R
Example : Self-bias configuration
GSQ
DQ
D
G
1. V
2. I
Det
3. V
e
rmine the following for
4. V
the network
5. Vs
Solutions:
D
GS D S
D GS D S
GS D S
When I = 4mA,
V = - I R
= - 4mA 1k =
When I = 8mA, V = - I R
V = - I R
= - 8 4m
-
A 1k
4V
= - 8V
Sketching the device characteristics
Vgs ID
0 IDSS
0.3Vp IDSS/2
0.5Vp IDSS/4
Vp 0 mA
Sketching the self-bias line
D GS
D GS
When I = 4mA, V =
When I = 8mA, V
- 4V
= - 8V
Graphical Solutions: Determining the Q-point
Q-point
IDQ=2.6mAVGSQ=-2.6mV
Mathematical Solutions
VVandmAIchoosetherefore
VV
kmAkmA
RIVRIV
mAImAI
IkI
kIII
MIkIkIm
kIm
kImI
V
RII
RIVrecallV
VII
GSD
SDGSSDGS
DD
DD
DDD
DDD
DDD
P
SDDSS
SDGSP
GSDSSD
6.2588.2;
6.29.13
)1(588.2)1(9.13
588.29.13
0288.01328
896288.036
1663636
8
6
)1(68
6
)1(18
)(1
1
211
2
2
2
22
2
2
Solutions
GSQV = - 2.6V
DQI = 2.6V
DS DD D D SV = V - I R + R
= 20V - 2.6mA 4.3kΩ
= 8.82V
G G S
D DS S D DD D S
DS S
V = V - V =
V = V + V or V = V - I R
= V + V = 8.82V + 2.6V
0V
11= .42V
S D SV = I R = 2.6mA 1kΩ
= 2.6V
IDQ = 2.6mA
Voltage-divider bias
A
IG=0A
Redrawn network
2G DD
1 2
RV = V
R + R
Sketching the network equation for the voltage-divider configuration.
D
GS
GS G I =0mA
GD
S V =0V
V = V
VI
R
G GS RS
GS G RS
GS G D SV
V - V - V = 0
V = V
= V - I
V
R
-
Effect of RS on the resulting Q-point.
Example : Voltage-divider bias
DQ GSQ
D
S
DS
DG
1. I andV
2. V
3. V
Determine the following for th
4. V
e netw k
5. V
or
Solutions
2G DD
1 2
DD2
RV = V
R + R
270kΩ 16V = V
2.1MΩ + 0.27MΩ
= 1.82V
D GSWhen I = 0mA, V = +1.82V
GS G D S
D
V = V - I R
= 1.82V - I 1.5kΩ
GS D
+1.82VWhen V = 0V, I = = 1.21mA
1.5kΩ
Determining the Q-point for the network
GS DV = 1.82V - I 1.5kΩ
IDQ=2.4mAVGSQ=-1.8mV
DS DD SS D S D
DS S
V = V + V - I R R
= V + V = 8.82V + 2 11.6V = .42V
solutions
• How to get IDS, VGS and VDS for voltage-divider bias configuration by using mathematical solutions?
Exercise 3:
DQ GSQ
DS
D
S
1. I andV
2. V
Determine the
followi
3. V
ng for the
networ
4. V
k
Drawing the self bias line
GS D S
GS D
V + I R -10V = 0
V = 10V - I 1.5k
D GSWhen I = 0mA, V = 10V
GS D
10VWhen V = 0V, I = = 6.67mA
1.5kΩ
Determining the Q-point
IDQ=6.9mAVGSQ=-0.35V DS DD SS D S DV = V - V - I R + R
= 20 +10 - (6.9mA)(1.8kΩ +1.5kΩ)
= 7.23V
D DD D DV = V - I R = 7.58V
S D DSV = V - V
= 7.58V - 7.23V = 0.35V
Exercise 4
D S
Determine the required
values of R and R
Determining VGSQ for the network.
DD DQRDD
DQ DQ
V VV 20V 12VR = =
I I 2.5mA
= 3.2k
GSQ
SDQ
V -1R = = 0.4k
I 2.5mA
FET (n-channel) Biasing Circuits
2
1
P
GSDSSDS V
VII
0, GGSGSGGGG IFixedVVRIV
DDSDDDS
P
GSDSSDS
RIVV
V
VII
and
12
S
GSDS
SDSGS
R
VI
RIV
0
For Self Bias Circuit
For Fixed Bias Circuit
Applying KVL to gate circuit we get
and
Where, Vp=VGS-off & IDSS is Short ckt. IDS
FET Biasing Circuits Count…
or Fixed Bias Ckt.
FET Self (or Source) Bias Circuit
2
1 and
P
GSDSSDS V
VII
S
GS
P
GSDSS R
V
V
VI
2
1
021
2
S
GS
P
GS
P
GSDSS R
V
V
V
V
VI
This quadratic equation can be solved for VGS & IDS
The Potential (Voltage) Divider Bias
01
2
S
GSG
P
GSDSS R
VV
V
VI
DSGSI V gives equation quadratic this Solving and
A Simple CS Amplifier and Variation in IDS with Vgs
FET frequency Analysis:
A common source (CS) amplifier is
shown to the right.
Rs Ci
RL
Co
CSS vi
vo
+
+
vs
+
_ _
_
io
ii
D
S
G
VDD
VDD
R1
RSS
RD
R2
The mid-frequency circuit is drawn as follows:
• the coupling capacitors (Ci and Co) and the
bypass capacitor (CSS) are short circuits
• short the DC supply voltage (superposition)• replace the FET with the hybrid-p model
The resulting mid-frequency circuit is shown
below.
Figure: Simple NMOS amplifier circuit and Characteristics with load line.
Figure: Drain characteristics and load line
For drawing an a c equivalent circuit of Amp.• Assume all Capacitors C1, C2, Cs as short circuit
elements for ac signal• Short circuit the d c supply• Replace the FET by its small signal model
Analysis of CS Amplifier
LgsmLoo
gs
ov
RvgRiv
v
vA
gain, Voltage
dDLLmgs
ov
rRRRgv
vA ,
Dd
DdDdo Rr
RrRrZ
imp., put Out
21 imp., Input RRRZ
Gin
A C Equivalent Circuit
Simplified A C Equivalent Circuit
Analysis of CS Amplifier with Potential Divider Bias
)R||(rgAv Ddm
DR10r D,m
dRgAv
)R||(rgAv Ddm
This is a CS amplifier configuration therefore the input is on the gate and the output is on the drain. 21 R||RZi
Dd R||rZo
DdD 10RrRZo
Application 1
The small signal equivalent circuit of CS Amp.
66
Application 2
67
Application 3
68
Application 4
69
Application 5
70
Application 6
71
Application: VIII
Application 7
72
Application 8
73
Application 9
FET Amplifier Configurations and
Relationships:
'' ' m L
vi m L m L 'm L
'L d D L d D L SS L
i Th SS Thm
o d D d D SSm
i i ivs vi vi vi
s i s i s i
i i iI vi vi vi
L L L
P vi I vi I
CS CG CD
g RA -g R g R
1 g R
R r R R r R R R R
1Z R R R
g
1Z r R r R R
g
Z Z ZA A A A
R + Z R + Z R + Z
Z Z ZA A A A
R R R
A A A A A
vi I
Th 1 2
A A
where R = R R
VCC
RD
S
R2
RSS
Rs Ci
RL
Co
C2
vi vo
+
+
vs
+
_
_ _
io ii
Common Gate (CG) Amplifier
R1
D
G
Note: The biasing circuit is the same for each amp.
Rs C i
vi
+
vs
+
_
_
ii G
VDD
VDD
R1
RSS
R2
Common Drain (CD) Amplifier (also called “source follower”)
RL
C o
vo
+
_
io
D
S