The top documents tagged [worstcase clock rate]

Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock Priyadharshini Shanmugasundaram priyas@nvidia.com Vishwani D. Agrawal.

Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock Priyadharshini Shanmugasundaram [email protected] Vishwani D. Agrawal.

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Priyadharshini Shanmugasundaram priyas@nvidia.com Vishwani D. Agrawal vagrawal@eng.auburn.edu DYNAMIC SCAN CLOCK CONTROL FOR TEST TIME REDUCTION MAINTAINING.

Priyadharshini Shanmugasundaram [email protected] Vishwani D. Agrawal [email protected] DYNAMIC SCAN CLOCK CONTROL FOR TEST TIME REDUCTION MAINTAINING.

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