Copyright © 2002 UCI ACES Laboratory aces A Design Space Exploration framework for rISA Design Ashok Halambi, Aviral Shrivastava,
Bypass Aware Instruction Scheduling for Register File Power Reduction Sanghyun Park 2 Aviral Shrivastava 1 Nikil Dutt 1 Alex Nicolau 1 Yunheung Paek 2.
Aggregating Processor Free Time for Energy Reduction Aviral Shrivastava 1 Eugene Earlie 2 Nikil Dutt 1 Alex Nicolau 1 1 Center For Embedded Computer Systems,
Copyright © 2005 UCI ACES Laboratory Kyoungwoo Lee, Nikil Dutt, and Nalini Venkatasubramanian ACES and DSM Donald Bren School.
Compiler-in-the-Loop ADL-driven Early Architectural Exploration Aviral Shrivastava 1 Nikil Dutt 1 Alex Nicolau 1 Eugene Earlie 2 1 Center For Embedded.
