Jsa
Vlsi Testing
Memory BIST.pdf
DESIGN OF LOW POWER TPG USING LP-LFSR
Fault simulation
Build-In Self-Test of FPGA Interconnect Delay Faults Laboratory for Reliable Computing (LaRC) Electrical Engineering Department National Tsing Hua University.
tpg_PRESTO.docx
By Praveen Venkataramani Committee Prof. Vishwani D. Agrawal (Advisor) Prof. Adit D. Singh Prof. Fa Foster Dai REDUCING ATE TEST TIME BY VOLTAGE AND FREQUENCY.
Linear feed back shift registers implemantation using vhdl
