Logic Design - Chapter 7: Sequential Circuit Analysis and Design
Asynchronous Circuits Jordi Cortadella Universitat Politècnica de Catalunya, Barcelona Collège de France May 14 th, 2013.
WP_100GbE
Elastic circuits Jordi Cortadella Universitat Politècnica de Catalunya, Barcelona EMicro 2013.
RTL Hardware Design by P. Chu Chapter 161 Clock and Synchronization.
1 Enhancing Performance of Iterative Heuristics for VLSI Netlist Partitioning Dr. Sadiq M. Sait Dr. Aiman El-Maleh Mr. Raslan Al Abaji. Computer Engineering.
RTL Hardware Design by P. Chu Chapter 81. 1. Overview on sequential circuits 2. Synchronous circuits 3. Danger of synthesizing asynchronous circuit 4.
1 Evolutionary Heuristics for Multiobjective VLSI Netlist Bi-Partitioning by Dr. Sadiq M. Sait Dr. Aiman El-Maleh Mr. Raslan Al Abaji Computer Engineering.
General Iterative Heuristics for VLSI Multiobjective Partitioning
Sequential Circuit Design: Principle
Evolutionary Heuristics for Multiobjective VLSI Netlist Bi-Partitioning
Clock and Synchronization
