Presenter : Ching-Hua Huang 2013/11/4 Temporal Parallel Simulation: A Fast Gate-level HDL Simulation Using Higher Level Models Cited count : 3 Dusung Kim.
Budapest University of Technology and Economics eet.bme.hu Department of Electron Devices A. Timár, M. Rencz Temperature dependent timing in standard cell.
Synchronous Parallel Environment for Emulation and Discrete-Event Simulation. The SPEEDES simulation engine allows the simulation builder to perform optimistic.
Temperature dependent timing in standard cell designs
