Dynamic Cache Management
Internal memory
Amd processor
Cache Design and Tricks Presenters: Kevin Leung Josh Gilkerson Albert Kalim Shaz Husain.
11/8/2005Comp 120 Fall 20051 8 November 9 classes to go! Read 7.3-7.5 Section 7.5 especially important!
1 Chapter Seven. 2 SRAM: –value is stored on a pair of inverting gates –very fast but takes up more space than DRAM (4 to 6 transistors) DRAM: –value.
1 HINT: A New Way to Measure Computer Performance John L. Gustafson and Quinn. O. Snell In Proceedings of the Fifth Annual Hawaii International Conference.
Improving Cache Performance.1 Review: The Memory Hierarchy Increasing distance from the processor in access time L1$ L2$ Main Memory Secondary Memory Processor.
1 SRAM: –value is stored on a pair of inverting gates –very fast but takes up more space than DRAM (4 to 6 transistors) DRAM: –value is stored as a charge.
Set-Associative Cache
8 November
