A Distributed Stallable Architecture to Handle Delay Variations
Physical Synthesis Buffer Insertion, Gate Sizing, Wire Sizing,
Yuchun Ma Joint Work with Jason Cong, Yongxiang Liu, Glenn Reinman, and Yan Zhang International Center for Design on Nanotechnologies Workshop.
DARPA Assessing Parameter and Model Sensitivities of Cycle-Time Predictions Using GTX u Abstract The GTX (GSRC Technology Extrapolation) system serves.
1 CDSC CHP Prototyping Yu-Ting Chen, Jason Cong, Mohammad Ali Ghodrat, Muhuan Huang, Chunyue Liu, Bingjun Xiao, Yi Zou.
Optimizing FPGA Accelerator Design for Deep Convolution neural Networks By: Mohamad Kanafanai.
NSF Workshop Electronic Design Automation Past, Present, and Future July 8-9, 2009 Sankar Basu, Robert Brayton, and Jason Cong,
Fall 2006EE 5301 - VLSI Design Automation I V-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part V: Placement.
1 Customizable Domain-Specific Computing Proposal for NSF “Expedition in Computing” Program Point of Contact: Prof. Jason Cong [email protected] Participating.
Medical Imaging Pipeline Yu-Ting Chen, Young-kyu Choi, Jason Cong, and Bingjun Xiao Center for Domain-Specific Computing Center for Future Architectures.
NSF Workshop Electronic Design Automation Past, Present, and Future July 8-9, 2009
