smnr2
Class 5 Interconnects 1
physical design essentials
EE 4271 VLSI Design, Fall 2011 Static Timing Analysis and Gate Sizing Optimization.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf Topics n Interconnect design. n Crosstalk. n Power optimization.
Lecture 10 - CpE 690 Introduction to VLSI Design
EE 4271 VLSI Design, Fall 2013
EE 4271 VLSI Design, Fall 2010
A Methodology for Interconnect Dimension Determination
An O(bn 2 ) Time Algorithm for Optimal Buffer Insertion with b Buffer Types
