Lecture 21 Last lecture –Cache Memory Direct mapping Fully associative Set associative Today’s lecture –Virtual memory Why virtual memory? Virtual address.
Memory Hierarchy Design Memory Hierarchy Design. 2 Outline Introduction Cache Basics Cache Performance Reducing Cache Miss Penalty Reducing Cache Miss.
1 Caches Concepts Review What is a block address? —Why not bring just what is needed by the processor? What is a set associative cache? Write-through?
Chap.7 Memory system
Cache Performance Metrics Miss Rate Fraction of memory references not found in cache (misses / accesses) = 1 – hit rate Typical numbers (in percentages):
ALPHA 21264 Introduction I- Stream ALPHA 21264 Introduction I- Stream Dharmesh Parikh.
Memory Hierarchy II. – 2 – Last class Caches Direct mapped E=1 (One cache line per set) Each main memory address can be placed in exactly one place in.
Cache Optimization for Real Time MPEG-4 ENCODER
