10/25/2007 ITC-07 Paper 26.31 Delay Fault Simulation with Bounded Gate Delay Model Soumitra Bose Design Technology, Intel Corp. Folsom, CA 95630 Hillary.
Copyright Agrawal, 2009ELEC5270-001/6270-001 Spr 09, Lecture 61 ELEC 5270/6270 Spring 2009 Low-Power Design of Electronic Circuits Power Analysis and Process.
Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering
Delay Fault Simulation with Bounded Gate Delay Model
