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Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs Hiroki Matsutani Michihiro Koibuchi Daisuke Ikebuchi Kimiyoshi Usami Hiroshi Nakamura.
A Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPs Hiroki Matsutani Yuto Hirata Michihiro Koibuchi Kimiyoshi Usami Hiroshi Nakamura Hideharu.
1 ECE-777 System Level Design and Automation Performance abstraction Cristinel Ababei Electrical and Computer Department, North Dakota State University.
The Design and Implementation of a Low-Latency On-Chip Network Robert Mullins 11 th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan.
L2 to Off-Chip Memory Interconnects for CMPs Presented by Allen Lee CS258 Spring 2008 May 14, 2008.
1 Lecture 21: Router Design Papers: Power-Driven Design of Router Microarchitectures in On-Chip Networks, MICRO’03, Princeton A Gracefully Degrading and.
Runtime Power Gating of On-Chip Routers Using Look-Ahead Routing Hiroki Matsutani (Keio Univ, Japan) Michihiro Koibuchi (NII, Japan) Daihan Wang (Keio.
Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs
