HLT architecture. TPC FEE anode wire pad plane drift region 88 s L1: 5 s 200 Hz PASA ADC Digital Circuit RAM 8 CHIPS x 16 CH / CHIP 8 CHIPS x 16 CH.
RCU Status 1.RCU design 2.RCU prototypes 3.RCU-SIU-RORC integration 4.RCU system for TPC test 2002 HiB, UiB, UiO.
HLT architecture
