Design and analysis of a two stage miller compensated
A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC Byung-Geun Lee, Member, IEEE, Byung-Moo Min, Senior Member, IEEE, Gabriele Manganaro, Senior.
NSoC 3DG Paper & Progress Report A 1.8-V 100-MS/s 12-bit Pipelined ADC Date ： 2009/03/05 Professor ： Ko-Chi Kuo Student ： Ting-Chang Ma.
