Download - Vlsi Unit 5 Notes

PRATHYUSHA INSTITUTE OF TECHNOLOGY AND MANAGEMNETDEPARTMENT OF ECE

CLASS: VII SEM, ECE

SUB. CODE/ SUB. NAME: EC 1401 /VLSI DESIGN

TOPICS COVERED:

UNIT III

SPECIFICATIONS USING VERILOG HDL:

(i) VLSI design Flow(ii) Identifiers(iii) Gate primitives(iv) Behavioral modeling(v) Switch Level Modeling(vi) Timing controls(vii) Procedural assignments (viii) Conditional Statements(ix) Structural and gate level description of Ripple carry adder, 3:8 Decoder,

Priority encoder, Comparator in Verilog .

PART A

1.What is HDL?

HDL stands for Hardware Description language. There are two types of HDL’s: VHDL – Very high speed Integrated circuit Hardware Description LanguageVerilog HDL

2.What is Verilog?Verilog is a general purpose hardware descriptor language. It is similar in syntax to the C

programming language. It can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the switch level.

3. What are the various modeling used in Verilog?(i). Gate-level modeling (Or) Structural modeling(ii). Data-flow modeling(iii) Switch-level modeling(iv)Behavioral modeling

4. What is structural gate-level modeling?Structural modeling describes a digital logic networks in terms of the components that

make up the system. Gate-level modeling is based on using primitive logic gates and specifying how they are wired together.

5. What is Switch-level modeling?Verilog allows switch-level modeling that is based on the behavior of MOSFETs.Digital

circuits at the MOS-transistor level are described using the MOSFET switches.Eg; nmos,pmos,cmos,rnmos,rpmos,rcmos

6. What are identifiers?Identifiers are names of modules, variables and other objects that we can reference in the

design. Identifiers consists of upper and lower case letters, digits 0 through 9, the underscore character(_) and the dollar sign($). It must be a single group of characters. Examples: A014, a ,b, in_o, s_outKeywords: Reserved Identifiers are known as Keywords. Eg: assign, module,endEscaped Identifiers : It is a way of providing printable ASCII characters and it starts with a \(backslash ) character.

7. What are the value sets in Verilog?Verilog supports four levels for the values needed to describe hardware referred to as

value sets.Value levels Condition in hardware circuits0 Logic zero, false condition1 Logic one, true conditionX Unknown logic valueZ High impedance, floating state

8. Give the classifications of timing control?Methods of timing control:

(i). Delay-based timing control(ii). Event-based timing control(iii) Level-sensitive timing control

Types of delay-based timing control:(i). Regular delay control(ii). Intra-assignment delay control(iii). Zero delay control

Types of event-based timing control:(i). Regular event control(ii). Named event control(iii). Event OR control(iv). Level-sensitive timing control

9. Give the different arithmetic operators?Operator symbol Operation performed Number of operands

* Multiply Two/ Divide Two+ Add Two- Subtract Two% Modulus Two** Power (exponent) Two

10. Give the different bitwise operators.Operator symbol Operation performed Number of operands~ Bitwise negation One& Bitwise and Two| Bitwise or Two^ Bitwise xor Two^~ or ~^ Bitwise xnor Two~& Bitwise nand Two~| Bitwise nor Two

11. What are gate primitives?Verilog supports basic logic gates as predefined primitives. Primitive logic function

keyword provide the basics for structural modeling at gate level. These primitives are nstantiated like modules except that they are predefined in verilog and do not need a module definition. The important operations are and, nand, or, xor, xnor, and buf(non-inverting drive buffer).

12. Define Pull gates.Pull gates have only one output with no inputs. There are two types of pull gates in

Verilog : pullup and pulldown.

Syntax : pullgate name <instance name>(output variable);Eg: pullup PUP(control);The output variable Control is assigned logic 1 always.

13. Give the two blocks in behavioral modeling.(i). An initial block executes once in the simulation and is used to set up initial conditions

and step-by-step data flow(ii). An always block executes in a loop and repeats during the simulation.

14. What are the types of typical gate delays in Verilog HDL?In real circuits, logic gates have delays associated with them:

(i) Rise delay(ii) Fall Delay(iii) Turn off delay

15. What are the types of conditional statements?1. No else statement

Syntax : if ( [expression] ) true – statement;2. One else statement

Syntax : if ( [expression] ) true – statement; else false-statement;

3. Nested if-else-ifSyntax : if ( [expression1] ) true statement 1;else if ( [expression2] ) true-statement 2;else if ( [expression3] ) true-statement 3;

else default-statement;The [expression] is evaluated. If it is true (1 or a non-zero value) true-statement is executed. If it is false (zero) or ambiguous (x), the false-statement is executed.

16.. Name the types of ports in VerilogTypes of port KeywordInput port InputOutput port OutputBidirectional port inout

17. What are the types of procedural assignments?1. Blocking assignment2. Non-blocking assignment

18.What is a task in Verilog?

A task is like a procedure that provides the ability to execute common piece of code from several different places in a description.

19. What is a continuous statement in Verilog HDL?

Continuous assignment statement is the most basic statement in Dataflow modeling used to drive a value onto a net.

Syntax : assign <delay> <variable> = expression;Eg: assign #5 sum = a^ b;

20. Why do you require sensitivity list?The sensitivity list is used to specify the event which flags off the execution of the

statements inside a block.Syntax : always @ (sensitivity list)Eg: (i)always @(posedge clock);

(ii)always @(a,b);

21. Give the basic syntax of Verilog HDL.

Syntax: module <module name > (Variable list);Input <variable list>;Output < variable list>;

.

.endmodule

Eg: module halfadder(a,b,sum,carry);

PART B

5. Explain in detail the VLSI design flow.(May 08/May 09)(12)

The flowchart of designing a VLSI circuit is given below:

Logic Design Process

Physical Design ProcessPhysical Layout

Design Specification

Behavioral Description

RTL Description

Functional Verification and Testing

Logic Synthesis /Timing Verification

Gate level Netlist

Logical Verification and Testing

Floor Planning /Automatic Place and route

Layout verification

Implementation

Design Specification:

In this stage, functionality, interface and overall architecture of the digital circuit to be

designed is described abstractly. Once the behavioral level design description is ready, it is tested

extensively with the help of a simulation tool.

Behavioral Description and RTL Description:

The design at this level has to be extended with the help of known functional blocks and

it is the next level of detailed description. Once again the design is tested for its

functionality.RTL description that is register transfer language explains the design in the form of

data flow.

Functional verification and Testing:

Design descriptions are tested for their functionality at every level - behavioral, data flow

and gate. This is to check whether al l the functions are carried out as expected and to rectify

them. This is carried out by the simulation tool.

Logic Synthesis:

The corresponding hardware realization of the circuit is carried at this level. The circuits

are realized through FPGA or ASIC. Logic synthesis converts the RTL description into gate

level net list.

Gate level net list:

A gate level net list is a description of the circuit in terms of gates and connections

between them. Logic synthesis tool ensures that the gate level net list meets timing, area and

power specifications.

PHYSICAL DESIGN:

Floor Planning:

In this step, the sizes of all the functional blocks are calculated and locations are

assigned. The main objective of this step is to keep the highly connected blocks physically close

to each other. Blocks with I/O pins are kept close to the periphery; those which interact

frequently are kept close together.

Placement:

The objectives of the placement step are:

Minimize the critical net delays

Make the chip as dense as possible

Minimize the power dissipation

Minimize the interconnect congestion

Minimize the timing requirement

Minimize cross talk

Minimize the interconnect length:

Routing:

Once the designer has floor planned a chip and the logic cells have been placed, it is time

to make the interconnections by routing the chip. There are two types of routing : Global routing

and Detailed routing The goal of the global router is to provide complete instructions to the

detailed router on where to route .The main objective of this step is to reduce the interconnect

length and area and to reduce the delays in the critical path.

Implementation:

Once the placement and routing are completed, the performance specifications are

computed and verified. After verification, the design of the VLSI circuit is implemented in an IC.

2.Write a note on gate primitives in Verilog HDL.(8 Marks )

Verilog HDL has the capability of gate level modeling. The following are the bult in primitive gates in VErilog HDL:(i) Multiple input gates: These gates have one or more than one input with one

output.Eg: or,and,nand,nor,xor,xnor

Syntax: multiple input gate type <instance name>(output A,input 1, input2…….,input n)

Eg: or or1(A,B,C,D,S1,);

(ii) Multiple output gates; These gates have only one input with multiple outputs. These gates can be used in an application where the output of a gate has to drive more than one load. Eg: buf,notSyntax: multiple output gate type <instance name>(input A,output 1, output2…….,ouyput n)Eg: buf buf1(A,S1, S2,S3);

(iii) Tristate gates; These gates have an additional control signal.The input is driven to the output only after the activation of the control signal.Eg: bufif0, bufif1, notif0, notif1Syntax: Tristate gate type <instance name>(input A, output B, Control C )Eg: bufif1 buffer(A,B,C);

(iv) Pull gates: These gates have only one output with no inputs. A pullup gate places

logic 1 on its output and a pulldown gate places a logic 0 on its output.Syntax : pullgate name <instance name>(output variable);Eg: pullup PUP(control);

The output variable Control is assigned logic 1 always.

(v) MOS switches: These gate models unidirectional switches,that is data flows from input to the output and the data flow can be turned off by appropriately setting the control input. These gates are used for switch level modeling in Verilog HDL. Eg: nmos, cmos, pmos, rcmos,Syntax: gate type<instance name>(output A, input B, Control C);Eg: nmos MOS1(Source,Drain,Gate)

(vi) Bidirectional Switches: These switches are bidirectional that is data flows from both ways and there is no delay when data propagates through the switches. Eg: tran, tranif0, tranif1Syntax: gate type<instance name>(signal A, signal B, Control C);

3.Write a note on Behavioral modeling .(May 08)

(OR)Explain structured procedure statements (OR) Write a note on always and initial statement

Ans. There are two structured procedure statements in Verilog HDL. They are always and initial. These statements are the two most basic statements in behavioral modeling. All other behavioral statements can appear only inside these structural procedure statements.

Initial statement: All statements inside an initial statement constitute an initial block. An initial block starts at time 0, executes once during a simulation and then does not execute again. If there are multiple initial blocks, each block starts to execute concurrently at time 0.Multiple behavioral statements can be grouped using the keywords begin and end.

Eg : initialX = 1’b1;

initial begin

M =2’b10;Y= 3’b001;

EndThe initial blocks are used for initialization, monitoring waveforms and other processes

that must be executed only once during the entire simulation run.

Always Statement: All behavioral statements inside an always statement constitute an always block. An always block starts at time 0, executes the statements in the always block continuously in a looping fashion. This statement is used to model a block of activity that is repeated continuously in a digital circuit. Consider a program to generate a clock signal :

Eg: module clockgen(clock);output reg clock;

initial clock = 1’b0;always

#5 clock = ~clock;endmodule

4.What are the procedural assignment statements?(OR) Differentiate Blocking and Non blocking statements.

Ans. (i) Blocking Assignments:

These statements are executed in the order they are specified in a sequential block. A blocking assignment will not block execution of statements that follow in a parallel block.

The “= “ operator is used to specify blocking assignments. Read and write operations are performed simultaneously. Eg: # 5 reg = 1’b0;

# 5 a = 2’b01;“a” will assigned to value 01 only after 10 time units.

(ii) Non- Blocking Assignments:

These statements are executed and processed at the same simulation time. The “<= “ operator is used to specify the Non-blocking assignments. Separate read and write operations are performed. A read operation is performed on

each right hand side variables and then the write operations are executed according to the scheduled time.

Eg: : # 5 reg = 1’b0; # 5 a = 2’b01;“a” will assigned to value 01 after 05 time units.

Application of Non- Blocking Assignments:

This is used to model several concurrent data transfer that takes place after a common event.

Separate read and write operation. These statements eliminate the race condition in digital circuits.

Eg; Consider a program for swapping the values of two registers:Case (i): using Blocking Assignments:

always @(posedge clock)a =b ;always @(posedge clock)b =a;In the above program blocking assignment is used . After the execution of first statement ‘b’ value is stored in ’ a’ and the original value of ‘a’ is lost and hence when the second statement is executed some value will be stored in ‘b’. Therefore swapping is not done in this case.

Case (i): using Non-Blocking Assignments:always @(posedge clock)a <=b ;always @(posedge clock)b <=a;In the above program Non blocking assignment is used . The values of ‘a’ and ‘b’ is first read and then assigned as per the instruction in the program. Therefore swapping is done in this case.

5.Explain the various timing control constructs available in Verilog HDL.(Dec 07)

Various timing controls are available in Verilog HDL. Timing controls provide a way to specify the simulation time at which procedural statements will execute. The symbol “# “ is used to specify the delay in a Verilog program. The various methods of timing control are :

(i) Delay based timing control: This timing control specifies in an expression specifies the time duration between when the statement is encountered and when the statement is executed. There are three types:

Regular delay control : This is used when a non-zero delay is specified to the left of a procedural assignment.Eg: # 10 y =1; # (4:5:6) q =0; Max.delay Typ.

Min Intra assignment delay control: Instead of specifying delay control to the of the

assignment , it is possible to assign delay to the right of the assignment operator. Such delay specifications alters the flow of activity in a different manner. Eg: reg x,y,z; initial begin x =0; z=0;y = # 5 x+z ; // Takes the value of x and z and evaluate x+z at zero time but assigns to y only after 5 time units.

Zero delay control : This isa method to ensure that a statement is executed last after all the statements in that simulation time are executed.Eg; reg x,y,z; initial begin x =0; z=0;endinitial begin # 0 x =1;#0 z=1;end // The statements x = 1 and z =1 will be executed last as they have a delay time as # 0.

(ii). Event based timing control : An event is the change in the value on a register or a net. Events can be used to trigger execution of a statement or a block of statements. There are four types of event based timing control : Regular event control, event OR control, named event control and level sensitive timing control.

Regular event control : The @ symbol is used to specify an event control. Statements can be executed on changes in signal value or at a positive or negative transition of the signal value. The keywords posedge and negedge are used for positive transition and negative transition respectively.Eg: q = @(posedge clock ) d;

Event OR control : This refers to transition on any of the multiple signals or events can trigger the execution of a statement or a block of statements.Eg: always @ (rest or clock or d) beginif (reset = = 0)

q = 1’b0;else q = 1’b1;

elseifend

Named event control: Verilog provides the capability to declare an event and then trigger and recognize the occurrence of that event . The event does not hold any data. Declaration by the keyword event and triggering the event by the symbol -> .Eg: event store data // name of the event is store dataalways @ (posedge clock) begin

if (data packet = = 4) -> store data // event store data is called again

Level sensitive Timing Control : Verilog HDL allows the ability to wait for a certain condition to be true before a statement or a block of statement is executed. The keyword wait is used for level sensitive onstructs.Eg: always wait ( count _enable) # 20 count = count +1 // the statement count +1 will be executed only when the signal count_enable is at logic 1.

6.(a) Write a Verilog program to simulate a 4 bit ripple carry adder by instantiating four full adders. (May 09/Dec 08/May 08//Dec 07)

Block Diagram Of 4 Bit Ripple carry adder:

B3 A 3

FA

B2 A 2

FA

B1

S3C4

C0

C3 C2 C1

S2 S1 S0

A 1

FA

B0 A

Veilog program

module RCA (a,b,c0, cout,s);

input [3:0]a;

output[3:0]b;

output[3:0]b;

wire (c1,c2,c3);

input c0;

output cout;

Fulladder fa1(s(0),c(1),a(0),b(0),c(0));




endmodule

module fulladder(a,b,c0,cout,s);

input a,b,c0;

output cout,s;

wire s1,s2,s3;

xor x1(s,a,b,c0);

and a1(s1,a,b);

and a2(s2,b,c0);

and a3(s3,c0,a);

or o1(cout,s1,s2,s3)

endmodule

(b)Write a Verilog program to simulate a 2-bit magnitude comparator(Dec 07)

module magcomp(a,b,c,d,e0;

input[1:0]a;

input[1:0]b;

output c:

output d;

output e;

wire(s1,s2,s3,s4,s5,x1,x2,s6,g1,g2,g3,l1,l2,l3);

not n1(s1,a[0]);

not n1(s2,a[1]);

not n1(s3,b[0]);

not n1(s4,b[1]);

xor x1(x1,a[0],b[0]);

not n5(s5,x1);

xor x2(x2,a[1],b[1]);

not n6(s6,x2);

and a1 (c,s5,s6);

and a2 (g1,a[1],s4);

and a3 (g2, a[0],s4,s3);

and a4 (g3, a[1], a[0],s3);

or o1(d,g1,g2,g3);

and a5(l1,s2,b[1]);

and a6 (l2,s1,b[1],b[0]);

and a7(l3,s2,s1,b[0]);

or o2(e,l1,l2,l3);

endmodule

7. Write a verilog program for 3:8 decoder.(Dec 08)

Truth Table for 3:8 decoder:

I1 I2 I3 01 02 03 04 05 06 07 080 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

O1 = I1bar .I2 bar .I3 bar

02 = I1bar .I2 bar .I3

O3 = I1bar .I2 .I3 bar

O4 = I1bar .I2 .I3

O5 = I1.I2 bar .I3 bar

O6 = I1 +I2bar +I3

O7 = I1b +I2 +I3 bar

O8 = I1 + I2 + I3

module 3:8 decoder(I1,I2,I3, O);

input I1,I2,I3;

output [7:0]O;

wire I1bar,I2 bar,I3 bar;

not n1(I1 bar,I1);

not n2(I2 bar,I2);

not n3(I3 bar,I3);

and(O[0],I1bar,I2bar,I3bar);

and(O[1],I1bar,I2bar,I3);

and(O[2],I1bar,I2,I3bar);

and(O[3],I1bar,I2,I3);

and(O[4],I1,I2bar,I3bar);

and(O[5],I1,I2bar,I3);

and(O[6],I1,I2,I3bar);

and(O[7],I1,I2,I3);

8. Explain the syntax of conditional statements in Verilog HDL with examples.(May 08)

(8 marks)

(i) If statement :

The if construct checks a specific condition and decides execution based on the result . The syntax of an if statement is:

if(condition 1)Expression 1;

elseif (condition 2)Expression 2;

elsedefault statement;

endifendifend

If condition 1 is satisfied or met with then expression 1 is evaluated ,otherwise it checks for the next condition, if satisfied expression 2 is evaluated .If none of the conditions are satisfied then a default statement is executed.

Eg: beginif (reset = = 0)

q = 1’b0;else q = 1’b1;

elseifend

(ii) Case Statement : A case statement is a multi way conditional branch. It has the following syntax: case( case_expression )

Case_expression condition 1 : statement 1;Case_expression condition 1 : statement 1;Case_expression condition 1 : statement 1;Case_expression condition 1 : statement 1;

default: statement;endcase

Eg: module mux(s,i0,i1,i2,i3,o);input i0,i1,i2,i3;input [1:0]s;output 0;

case(s)2’b00:0=i0;2’b01:0=i1;2’b10:0=i2;2’b11:0=i3;

endcaseendmodule

9. Write a note on switch level modeling.(May ’08)(8 Marks)Switch level modeling forms the bsic level of modeling digital circuits. The MOS

transistor is the basic element around which a VLSI circuit is built. The switches are available as primitive in Verilog. By successive instantiation of these switches ,logic gates can be realized.

Switch modeling elements:(i) MOS switch(ii) CMOS switch(iii) Bidirectional switches(iv) Power and Ground(v) Resistive switches(vi) Pull up and pull down

(i) MOS switches: These gate models unidirectional switches,that is data flows from input to the output and the data flow can be turned off by appropriately setting the control input. These gates are used for switch level modeling in Verilog HDL. Eg: nmos, pmos,

Syntax: gate type<instance name>(output A, input B, Control C);Eg: nmos MOS1(Source,Drain,Gate)

(ii ) CMOS Switches: A CMOS switch is formed by connecting a PMOS and NMOS switch in parallel. The input pins are connected in one side and the output pins are connected in the other. P_control turns the PMOS ON when it is in the logic state 0. N_control turns the NMOS ON when it is in the logic state 1.

Syntax: gate type<instance name>( out,in,P_control,N_control);Eg: cmos MOS1(out,in,P_control,N_control)

(iii) Bidirectional Switches: These switches are bidirectional that is data flows from both ways and there is no delay when data propagates through the switches. Eg: tran, tranif0, tranif1

Syntax: gate type<instance name>(signal A, signal B, Control C);

(iv) Pull gates: These gates have only one output with no inputs. A pullup gate places logic 1 on its output and a pulldown gate places a logic 0 on its output.

Syntax : pullgate name <instance name>(output variable);Eg: pullup PUP(control);The output variable Control is assigned logic 1 always

(v) Power and Ground : Power and ground sources are specified by the keywords supply 1 and supply 0.

(vi) Resistive Switches: These switches have higher source to drain impedance than regular switches and reduce the strength of the signal passing through them.

Eg: rnmos,rpmos

10. Write a Verilog code for a priority encoder.(8 marks)

The truth table of priority encoder is shown below:

a[0] a[1] a[2] a[3] b[0] b[1]1 0 0 0 0 0x 1 0 0 0 1x x 1 0 1 0x x x 1 1 1

b[0) = a[3] +a[2]

b[1] = a[3] +a[1]a[2]

module priority(a,b);

input([3:0]a;

output[1:0]b;

wire d1,d2;

or o1(b[0],a[2],a[3]);

and a1 (d1,a[1],a[2]);

not n1(d2,d1);

or o2 (b[1],a[3],d[2]);

endmodule