Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 11
ELEC 5270-001/6270-001 (Fall 2006)ELEC 5270-001/6270-001 (Fall 2006)Low-Power Design of Electronic CircuitsLow-Power Design of Electronic Circuits
(Formerly ELEC 5970-003/6970-003)(Formerly ELEC 5970-003/6970-003)
Dual-Threshold Low-Power DevicesDual-Threshold Low-Power Devices
Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor
Department of Electrical and Computer Department of Electrical and Computer EngineeringEngineering
Auburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849http://www.eng.auburn.edu/~vagrawalhttp://www.eng.auburn.edu/~vagrawal
[email protected]@eng.auburn.edu
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 22
Subthreshold ConductionSubthreshold ConductionVgs – Vth -Vds
Ids = I0 exp( ───── ) × (1– exp ── ) nVT VT
Sunthreshold slope
0 0.3 0.6 0.9 1.2 1.5 1.8 V Vgs
Ids
1mA100μA10μA1μA
100nA10nA1nA
100pA10pA
Vth
Sub
thre
shol
dre
gion
Saturation region
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 33
Thermal Voltage, Thermal Voltage, vvTT
VT = kT/q = 26 mV, at room temperature.
When Vds is several times greater than VT
Vgs – Vth Ids = I0 exp( ───── )
nVT
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 44
Leakage CurrentLeakage Current Leakage current equals Leakage current equals IIdsds when when VVgsgs= 0= 0 Leakage current, Leakage current, IIdsds = = II00 exp(exp(-V-Vthth/nV/nVTT)) At cutoff, At cutoff, VVgsgs = = VVth th , and , and IIdsds = = II00
Lowering leakage to 10Lowering leakage to 10--bbII00
VVthth = = bnVbnVT T ln 10 = 1.5ln 10 = 1.5b b × 26 ln 10 = 90× 26 ln 10 = 90bb mVmV
Example: To lower leakage to Example: To lower leakage to II00/1,000/1,000
VVthth = 270 mV = 270 mV
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 55
Threshold VoltageThreshold Voltage VVthth = = VVt0t0 + + γγ[([(ΦΦss++VVsbsb))½½- - ΦΦss
½½]] VVt0t0 is threshold voltage when source is at is threshold voltage when source is at
body potential (body potential (0.4 V for0.4 V for 180nm process180nm process)) ΦΦs s = = 22VVTT ln(ln(NNA A /n/ni i )) is surface potentialis surface potential γγ = (2 = (2qqεεsi si NNAA))½½ttox ox //εεoxox is body effect is body effect
coefficient (0.4 to 1.0)coefficient (0.4 to 1.0) NNAA is doping level = is doping level = 8×108×101717 cm cm-3-3
nnii = = 1.45×101.45×101010 cm cm-3-3
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 66
Threshold Voltage, Threshold Voltage, VVsbsb=1.1V=1.1V Thermal voltage, Thermal voltage, VVTT = = kT/qkT/q = 26 mV = 26 mV ΦΦss = 0.93 V = 0.93 V εεoxox = 3.9×8.85×10 = 3.9×8.85×10-14-14 F/cm F/cm εεsisi = 11.7×8.85×10 = 11.7×8.85×10-14-14 F/cm F/cm ttoxox = 40 A = 40 Aoo
γγ = 0.6 V = 0.6 V½½
VVthth = = VVt0t0 + + γγ[([(ΦΦss++VVsbsb))½½- - ΦΦss½½] = 0.68 V] = 0.68 V
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 77
A Sample CalculationA Sample Calculation
VVDDDD = 1.2V, 100nm CMOS process = 1.2V, 100nm CMOS process Transistor width, W = 0.5Transistor width, W = 0.5μμmm OFF device (OFF device (VVgsgs = = VVthth) leakage) leakage
II00 = 20nA/ = 20nA/μμm, for low threshold transistorm, for low threshold transistor II00 = 3nA/ = 3nA/μμm, for high threshold transistorm, for high threshold transistor
100M transistor chip100M transistor chip Power = (100×10Power = (100×1066/2)(0.5×20×10/2)(0.5×20×10-9-9A)(1.2V) = A)(1.2V) =
600mW 600mW for all low-threshold transistorsfor all low-threshold transistors Power = (100×10Power = (100×1066/2)(0.5×3×10/2)(0.5×3×10-9-9A)(1.2V) = A)(1.2V) =
90mW 90mW for all high-threshold transistorsfor all high-threshold transistors
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 88
Dual-Threshold ChipDual-Threshold Chip
Low-threshold only for 20% Low-threshold only for 20% transistors on critical path.transistors on critical path.
Leakage power Leakage power = 600×0.2 + = 600×0.2 + 90×0.890×0.8
= 120 + 72= 120 + 72
= 192 mW= 192 mW
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 99
Dual-Threshold CMOS Dual-Threshold CMOS CircuitCircuit
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 1010
Dual-Threshold DesignDual-Threshold Design To maintain performance, all gates on To maintain performance, all gates on
the critical path are assigned low the critical path are assigned low VVth th .. Most of the other gates are assigned Most of the other gates are assigned
high high VVth th . But,. But, Some gates on non-critical paths may Some gates on non-critical paths may
also be assigned low also be assigned low VVthth to prevent to prevent those paths from becoming critical.those paths from becoming critical.
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 1111
Integer Linear Programming (ILP) Integer Linear Programming (ILP) to Minimize Leakage Powerto Minimize Leakage Power
Use dual-threshold CMOS processUse dual-threshold CMOS process First, assign all gates low First, assign all gates low VVthth
Use an ILP model to find the delay (Use an ILP model to find the delay (TTcc) of the ) of the critical pathcritical path
Use another ILP model to find the optimal Use another ILP model to find the optimal VVthth assignment as well as the reduced leakage assignment as well as the reduced leakage power for all gates without increasing power for all gates without increasing TTcc
Further reduction of leakage power possible by Further reduction of leakage power possible by letting letting TTcc increase increase
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 1212
ILP -ILP -VariablesVariables For each gate For each gate ii define two variables. define two variables. TTi i : : the longest time at which the the longest time at which the
output of gate output of gate ii can produce an event can produce an event after the occurrence of an input event after the occurrence of an input event at a primary input of the circuit. at a primary input of the circuit.
XXi i :: a variable specifyinga variable specifying low or high low or high VVthth for gate for gate i i ;; X Xii is an integer [0, 1], is an integer [0, 1],
1 1 gate gate ii is assigned low is assigned low VVth th ,,
0 0 gate gate ii is assigned high is assigned high VVth th ..
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 1313
ILP - ILP - objective functionobjective function
minimize the sum of all gate leakage currents, minimize the sum of all gate leakage currents, given by given by
IILi Li is the leakage current of gate is the leakage current of gate ii with low with low VVthth IIHiHi is the leakage current of gate is the leakage current of gate ii with high with high VVthth Using SPICE simulation results, construct a Using SPICE simulation results, construct a
leakage current look up table, which is indexed leakage current look up table, which is indexed by the gate type and the input vectorby the gate type and the input vector . .
i
leakiddleak IVP
i
HiiLii IXIXMin 1
Leakage power:
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 1414
ILP - ILP - ConstraintsConstraints For each gateFor each gate
(1)(1)
output of gate output of gate jj is fanin of gate is fanin of gate ii
(2) (2)
Max delay constraints for primary outputs Max delay constraints for primary outputs (PO)(PO)
(3) (3)
TTmaxmax is the maximum delay of the critical path is the maximum delay of the critical path
HiiLiiji DXDXTT 1
10 iX
maxTTi
Gate j
Gate i
Tj
Ti
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 1515
ILP Constraint ExampleILP Constraint Example
Assume all primary input (PI) signals on the left arrive at Assume all primary input (PI) signals on the left arrive at the same time. the same time.
For gate 2, constraints areFor gate 2, constraints are
0
3
1
2
222202 1 HL DXDXTT
22222 10 HL DXDXT
HiiLiiji DXDXTT 1
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 1616
ILP – Constraints (cont.)ILP – Constraints (cont.)
DDHi Hi is the delay of gateis the delay of gate i i with highwith high V Vthth
DDLi Li is the delay of gateis the delay of gate i i with lowwith low V Vthth
A second look-up table is constructed A second look-up table is constructed and specifies the delay for given gate and specifies the delay for given gate type and fanout number. type and fanout number.
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 1717
ILP – Finding Critical DelayILP – Finding Critical Delay
TTmaxmax can be specified or be the delay of longest path can be specified or be the delay of longest path ((TTcc).).
To find To find TTc c , we change constraints (2) to an equation, , we change constraints (2) to an equation, assigning all gates low assigning all gates low VVthth
Maximum Maximum TTii in the ILP solution is in the ILP solution is TTcc.. If we replace If we replace TTmaxmax with with TTc c , the objective function , the objective function
minimizes leakage power without sacrificing minimizes leakage power without sacrificing performance.performance.
10 iX
maxTTi
1iX
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 1818
Power-Delay TradeoffPower-Delay Tradeoff If we gradually increase If we gradually increase TTmaxmax from from TTc c , ,
leakage power is further reduced, because leakage power is further reduced, because more gates can be assigned high more gates can be assigned high VVth th ..
But, the reduction trends to become But, the reduction trends to become slower.slower.
When When TTmax max = = (130%)(130%) T Tcc , the reduction , the reduction about levels off because almost all gates about levels off because almost all gates are assigned high are assigned high VVth th . .
Maximum leakage reduction can be 98%. Maximum leakage reduction can be 98%.
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 1919
Power-Delay TradeoffPower-Delay Tradeoff
1 1.1 1.2 1.3 1.4 1.5
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Normalized Critical Path Delay
Nor
mal
ized
Lea
kage
Pow
er
C432
C880
C1908
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 2020
Leakage ReductionLeakage Reduction
CircuitCircuitNumbeNumbe
r of r of gates gates
TTcc
(ns) (ns)
UnUnoptimizeoptimize
ddIIleakleak (μA) (μA)
OptimizeOptimized d
IIleakleak (μA) (μA)
((TTmaxmax=T=Tcc))
LeakageLeakageReductioReductio
nn%%
Sun Sun OS 5.7 OS 5.7 CPU s CPU s
OptimizedOptimizedIIleakleak (μA) (μA)
((TTmaxmax==1.251.25TTcc
))
Leakage Leakage Reduction Reduction
%%
SunSunOS 5.7 OS 5.7 CPU s CPU s
C432C432 160160 0.750.75 2.6202.620 1.0221.022 61.061.0 0.250.25 0.1320.132 95.095.0 0.250.25
C499C499 182182 0.390.39 4.2934.293 3.4643.464 19.319.3 0.310.31 0.2250.225 94.894.8 0.300.30
C880C880 328328 0.670.67 4.4064.406 0.5240.524 88.188.1 0.540.54 0.1530.153 96.596.5 0.530.53
C1355C1355 214214 0.400.40 4.3884.388 3.2903.290 25.025.0 0.330.33 0.2940.294 93.393.3 0.360.36
C1908C1908 319319 0.570.57 6.0236.023 2.0232.023 66.466.4 0.570.57 0.2040.204 96.696.6 0.560.56
C2670C2670 362362 1.261.26 5.9255.925 0.6590.659 90.490.4 0.680.68 0.1250.125 97.997.9 0.530.53
C3540C3540 10971097 1.751.75 15.62215.622 0.9720.972 93.893.8 1.711.71 0.3190.319 98.098.0 1.701.70
C5315C5315 11651165 1.591.59 19.33219.332 2.5052.505 87.187.1 1.821.82 0.3950.395 98.098.0 1.831.83
C6288C6288 11771177 2.182.18 23.14223.142 6.0756.075 73.873.8 2.072.07 0.6780.678 97.197.1 2.002.00
C7552C7552 10461046 1.921.92 22.04322.043 0.8720.872 96.096.0 1.591.59 0.4450.445 98.098.0 1.681.68
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 2121
Dynamic & Leakage Power Dynamic & Leakage Power ComparisonComparison
VVTT (thermal voltage, (thermal voltage, kT/qkT/q) and ) and VVthth (threshold voltage) (threshold voltage) both depend on the temperature; leakage current also both depend on the temperature; leakage current also strongly depends on temperature.strongly depends on temperature.
Spice simulation shows that for a 2-input NAND gate Spice simulation shows that for a 2-input NAND gate
- with low - with low VVth th , , IIsubsub @ 90ºC = 10 × @ 90ºC = 10 × IIsubsub @ 27ºC @ 27ºC
- with high - with high VVth th , , IIsubsub @ 90ºC = 20 × @ 90ºC = 20 × IIsubsub @ 27ºC @ 27ºC To manifest the projected contribution of leakage to the To manifest the projected contribution of leakage to the
total power, we compare dynamic and leakage power @ total power, we compare dynamic and leakage power @ 90ºC.90ºC.
t
ds
th
gsth
eff
effoxsub V
V
nv
VVev
L
WCuI
t
exp1exp8.120
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 2222
Dynamic & Leakage Power Dynamic & Leakage Power Comparison (cont.)Comparison (cont.)
Without considering glitches, the Without considering glitches, the dynamic power is estimated by an dynamic power is estimated by an event driven simulator, and is given byevent driven simulator, and is given by
We apply 1000 random test vectors at We apply 1000 random test vectors at PIs with a vector period of 120% PIs with a vector period of 120% TTc c , , and calculate the total number of and calculate the total number of weighted (by node capacitance) weighted (by node capacitance) transitions in the circuit. transitions in the circuit.
c
ii
iddinvdyn
dyn T
FOTVC
T
EP
2.11000
5.0 2
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 2323
Dynamic & Leakage Power Dynamic & Leakage Power @90@90ooCC
CircuiCircuitt
PPdyndyn
(μW)(μW)PPleak1leak1
(μW)(μW)
PPleak1leak1/ /
PPdyn dyn %%PPleak2leak2
(μW)(μW)PPleak2leak2/ /
PPdyn dyn %%
C432C432 71.1771.17 26.2026.20 36.836.8 10.2210.22 14.314.3
C499C499 149.81149.81 42.9342.93 28.728.7 34.6434.64 23.123.1
C880C880 135.19135.19 44.0644.06 32.632.6 5.245.24 3.83.8
C135C13555
162.39162.39 43.8843.88 27.027.0 32.9032.90 20.320.3
C190C19088
185.60185.60 60.2360.23 33.433.4 20.2320.23 10.910.9
C267C26700
92.6492.64 59.2559.25 64.064.0 6.596.59 7.17.1
C354C35400
218.41218.41 156.22156.22 71.571.5 9.729.72 4.44.4
C531C53155
299.61299.61 193.32193.32 64.664.6 25.0525.05 8.48.4
C628C62888
215.12215.12 231.42231.42 108.0108.0 60.7560.75 28.228.2
C755C75522
229.13229.13 220.43220.43 96.296.2 8.728.72 3.83.8
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 2424
Dynamic & Leakage Power Dynamic & Leakage Power @90@90ooCC
Pow
er
in μ
W
Fall 06, Sep 14Fall 06, Sep 14 ELEC5270-001/6270-001 Lecture 5ELEC5270-001/6270-001 Lecture 5 2525
SummarySummary Leakage power is a significant fraction of Leakage power is a significant fraction of
the total power in nanometer CMOS devices.the total power in nanometer CMOS devices. Leakage power increases with temperature; Leakage power increases with temperature;
can be as much as dynamic power.can be as much as dynamic power. Dual threshold design can reduce leakage.Dual threshold design can reduce leakage.
Reference: Y. Lu and V. D. Agrawal, “Leakage Reference: Y. Lu and V. D. Agrawal, “Leakage and Dynamic Glitch Power Minimization Using and Dynamic Glitch Power Minimization Using Integer Linear Programming for Integer Linear Programming for VVthth Assignment Assignment and Path Balancing,” and Path Balancing,” Proc. PATMOSProc. PATMOS, 2005, pp. , 2005, pp. 217-226, access paper at217-226, access paper at http://www.eng.auburn.edu/~vagrawal/TALKS/PATMOS-13http://www.eng.auburn.edu/~vagrawal/TALKS/PATMOS-134.pdf4.pdf
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