Download - VESA DSC 1.1 Applications Video Decoder IP Coreww1.prweb.com/prfiles/2015/09/29/13123832/Hardent... · 9/29/2015  · VESA DSC 1.1 Video Decoder IP Core Copyright © 2015 Hardent

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VESA DSC 1.1Video DecoderIP Core

www.hardent.com Copyright © 2015 Hardent Inc.

For additional information contact: [email protected]+1-514-284-5252

Key Features

• VESA DSC 1.1 compliant• Supports all DSC 1.1 mandatory and optional encoding mechanisms o MMAP, BP, MPP and ICH• Input buffering compatible with transport stream over video interfaces• Con�gurable maximum display resolution o Up to 4K (4096x2160), 5K (UHD+) and 8K (FUHD)• 8 and 10 bits video components• YCbCr and RGB 4:4:4 video output format• Optional downsampling 4:4:4 to 4:2:2 at output• Resilient to bitstream corruption• 3 pixels / clock internal processing architecture• Parameterizable number of parallel slice decoder instances (1, 2 or 4) to adapt to the capability of the technology and target display resolutions used• Optional DSC features can be disabled to improve area• 100% veri�cation coverage based on UVM environment• Veri�ed against the VESA DSC 1.1 C model using a comprehensive test image library

Deliverables

• Encrypted RTL source code IP core• Functional and structural coverage reports• Comprehensive integration guide• Technical support and maintenance updates

Product options

• RTL source code• IP customization and integration services available on request• Multi-projects and perpetual licenses available• UVM veri�cation bindable modules• FPGA evaluation and prototyping platform

Hardent provides IP solutions as well as cutting-edge ASIC and FPGA design services for electronics manufacturers using display technology. As a member of VESA and a key contributor of the DSC Task Group, Hardent has used its expertise and skills to develop the very latest standards in display technology. Hardent’s high-quality IPs enable clients to accelerate their development schedules and meet demanding time-to-market deadlines.

Transport Link

Pixel busto LCD panel

DisplayReceiver

Slice Demultiplexcontroller

Rasterization Bu�ers

LineBu�ers

CompressedData Bu�ers

N = 1,2 or 4

DSC DecoderHard Slice

Instance #N

LCD Receiver Logic

Hardent DSC Decoder IP

Applications• Mobiles

• Tablets• 4K / UHD TVs

• Broadcast video• Video transmission

• In-car video applications

VESA DSC 1.1Video EncoderIP Core

www.hardent.com Copyright © 2015 Hardent Inc.

For additional information contact: [email protected]+1-514-284-5252

Key Features

• VESA DSC 1.1 compliant• Supports all DSC 1.1 mandatory encoding mechanisms o MMAP, BP, MPP and ICH• Output buffering compatible with transport stream over video interfaces• Parameterizable number of output video interfaces• Con�gurable maximum display resolution o Up to 4K (4096x2160), 5K (UHD+) and 8K (FUHD)• 8 and 10 bits video components• YCbCr and RGB 4:4:4 video input format• Optional upsampling 4:2:2 to 4:4:4 at input• 1 pixel / clock internal processing architecture• Parameterizable number of parallel slice encoder instances (1, 2 or 4) to adapt to the capability of the technology and target display resolutions used• Multiple slices per line in each encoder instance supported• 100% veri�cation coverage based on UVM environment• Veri�ed against the VESA DSC 1.1 C model using a comprehensive test image library

Deliverables

• Encrypted RTL source code IP core• Functional and structural coverage reports• Comprehensive integration guide• Technical support and maintenance updates

Product options

• RTL source code• IP customization and integration services available on request• Multi-projects and perpetual licenses available• UVM veri�cation bindable modules• FPGA evaluation and prototyping platform

Hardent DSC Encoder IP

DisplayTransmitter(s)

DSCCompliantBitstreams

Slices MultiplexingController

De-rasterization Bu�ers

Incoming pixels

LineBu�ers

Multiple CompressedData Bu�ers

N = 1,2 or 4

DSC EncoderHard Slice

Instance #N

Applications• Mobiles

• Tablets• 4K / UHD TVs

• Broadcast video• Video transmission

• In-car video applications

Hardent provides IP solutions as well as cutting-edge ASIC and FPGA design services for electronics manufacturers using display technology. As a member of VESA and a key contributor of the DSC Task Group, Hardent has used its expertise and skills to develop the very latest standards in display technology. Hardent’s high-quality IPs enable clients to accelerate their development schedules and meet demanding time-to-market deadlines.