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Vertical field effect tunneling transistor based on graphene-ultrathin Si nanomembrane

heterostructures

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2015 2D Mater. 2 044006

(http://iopscience.iop.org/2053-1583/2/4/044006)

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2DMater. 2 (2015) 044006 doi:10.1088/2053-1583/2/4/044006

PAPER

Vertical field effect tunneling transistor based on graphene-ultrathinSi nanomembrane heterostructures

TanmoyDas,Houk Jang, Jae Bok Lee,HyunwooChu, SeongDaeKim and Jong-HyunAhnSchool of Electrical and Electronic Engineering, Yonsei University, Seoul, 120-749, Korea

E-mail: ahnj@yonsei.ac.kr

Keywords: graphene, Si nanomembrane, tunneling transistor, heterostructures

AbstractGraphene-based heterostructured vertical transistors have attracted a great deal of research interest.Hereinwe propose a Si-based technology platform for creating graphene/ultrathin semiconductor/metal (GSM) junctions, which can be applied to large-scale and low-power electronics compatiblewith a variety of substrates.We fabricated graphene/Si nanomembrane (NM)/metal verticalheterostructures by using a dry transfer technique to transfer SiNMs onto chemical vapor deposition-grown graphene layers. The resulting van derWaals interfaces between graphene and p-SiNMsexhibited nearly ideal Schottky barrier behavior. Due to the low density of states of graphene, thegraphene/SiNMSchottky barrier height can bemodulated bymodulating the band profile in thechannel region, yieldingwell-defined currentmodulation.We obtained amaximum current on/offratio (Ion/Ioff) of up to∼10

3, with a current density of 102 A cm−2.We also observed significantdependence of Schottky barrier heightΔjb on the thickness of the SiNMs.We confirmed that thetransport in these devices is dominated by the effects of the graphene/SiNMSchottky barrier.

1. Introduction

Recent rapid progress in basic science and applicationsof graphene has opened the way for materials just oneatom thick to be used in future electronics, includingdevices with new structures. Graphene’s unique physi-cal properties, such as its two-dimensional structure,high carriermobility, and low density of states, make itattractive for high-speed electronic devices [1–5].However, graphene-based field-effect transistors can-not be completely switched off due to the lack of anintrinsic band gap in graphene; hence, they areinappropriate for digital logic applications [6, 7]. Onthe other hand, heterostructures based on grapheneand other two-dimensional crystals have been demon-strated that can be assembled into three-dimensionalstacks with atomic-layer precision; these have shown avariety of fascinating physical phenomena and havearoused immense interest in demonstrating a proto-typefield-effect tunneling transistor, which is regardedas a candidate technology to replace complementarymetal-oxide semiconductor technology [6, 8, 9]. Inparticular, various vertically layered heterostructuresbased on work function tunability of graphene have

been studied recently, such as graphene-based tunnel-ing transistors (called barristors) and vertical field-effect transistors (VFETs); these have shown improvedIon/Ioff characteristics compared to planar graphenefield-effect devices [10, 11]. The demonstration ofsuch vertically stacked heterostructures has opened uppotential high-performance applications in tunnelingtransistors, photovoltaic cells, and flexible devicesbased on two-dimensional (2D) materials. A broadrange of possible materials can be incorporated intosuch stacks by weak van der Waals forces to createnovel highly tailored heterostructures [3, 15, 16]. Tocreate VFET heterojunctions, various kinds of 2Dbarrier materials have been considered, such asexfoliated hexagonal boron nitride, molybdenumdisulfide, and tungsten disulfide, but critical challengesstill remain forwafer-scale integration [12, 13, 17].

On the other hand, single-crystal Si NMs, formedin large sheets with precisely defined thicknesses com-parable to 2D materials, offer unique advantages overother transition-metal dichalcogenides. Si NMs arecompatible with established semiconductor techni-ques, and can have exceptional material quality, com-positional purity, and high uniformity, leading to

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© 2015 IOPPublishing Ltd

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straightforward paths for wide-scale integration intoexisting Si-based technology platforms. Transferrablesingle-crystal Si NMs are often more suitable thanother 2D materials for use as active materials in flex-ible electronics due to their material uniformity,mechanical flexibility and durability, electrical proper-ties equivalent to their bulk counterparts, easy hand-ling and processing, and low cost [18–22]. There is abroad range of electronics applications in whichmechanically flexible materials with higher speed areneeded; these applications include flexible electronicsand optoelectronics, including transparent electro-nics. Because the thickness of Si NMs is controllable,their use may allow this range of applications to beextended.

Herein we describe a new generation of verticaltunneling transistors in which ultrathin Si NMs serveas an ultrathin 2D barrier material between chemicalvapor deposition (CVD)-grown graphene and a metalelectrode. By utilizing the Schottky barrier heightbetween graphene and Si NMs in ultrathin Si-basedtunneling transistors, the device characteristics can beimproved considerably, to the extent that the resultingdevice can satisfy the requirements for next-genera-tion electronic devices. Ultrathin Si NMs offer distinctadvantages over other 2D materials, including theirchemical stability and moderate band gaps. Addition-ally, the use of the dry transfer technique with Si NMscan produce a clean interface between graphene and SiNMs that exhibits nearly ideal Schottky diode beha-vior, thereby yielding strong current rectification.

2. Experimentalmethods

Figure 1(a) schematically illustrates a typical verticaltransistor of our design. The fabrication techniquesfor the vertical transistor are schematically illustratedin the methods section. Briefly, monolayer graphenewas first grown by CVD and transferred onto a siliconwafer with a SiO2 layer 285 nm thick [23]. Then, thetransferred graphene layer was patterned by photo-lithography and oxygen plasma etching into strips

25 μm wide and 100 μm long to define the drainelectrode. SiNMsof various thicknesseswere preparedfrom commercial silicon-on-insulator (SOI)wafers, aspreviously reported [21]. Before transferring a Si NMonto the graphene, the native oxide on the exposed Sisubstrate was carefully removed by additional wetetching, and the Si surface was then passivated byhydrogen treatment. Then, the Si NM surface wastreated with a UV ozone treatment to form a thinsurface passivation layer, and the passivated Si NMwas stacked onto the graphene contact by means of adry transfer technique [24]. The top metal electrodewas formed by electron-beam lithography and thermalevaporation of Ni/Au (20/30 nm) onto the Si NMs tooverlap the bottom graphene electrode. We studiedmore than a dozen graphene/Si NM heterostructureswith a diverse range of thicknesses from 8 to 100 nm,and observed qualitatively similar behavior for eachbatch of devices.

3. Results and discussion

Figure 1(b) shows an optical image of a fabricateddevice. The 25 μm strip of monolayer graphene islocated inside the dotted lines. The total channel areais defined by the area of overlap between the grapheneand the top metal electrode. A cross-sectional trans-mission electron microscope (TEM) image showingthe region from the top drain electrode to the bottomsource electrode was taken to investigate the overallintegration of the graphene/Si NM/top electrodevertical stack, and to study the interface (figure 1(c)).The well-optimized transfer process including surfacepre-treatment produced clean interfaces betweengraphene and Si, free from native oxide or othercontamination layers. In a larger-area TEM image ofunoptimized Si NMs transferred onto graphene,contamination was observed, as was native oxidebetween the graphene and Si (supplementary informa-tion). Reducing damage to the silicon substrate duringthe wet etching of silicon oxide was identified as a keyfactor in producing atomically clean interfaces.

Figure 1.Graphene/SiNMheterostructure layout: (a)Three-dimensional schematic illustration of the vertically stacked graphene/SiNM/metal transistor. (b)Optical image of a typical vertical transistor device (scale bar: 40 μm). (c)Cross-sectional TEM image of avertical transistor (scale bar: 2 nm).

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The characteristics of current density versus vol-tage (J–V) were measured at different gate voltages(Vg) in graphene/Si NM/Ni vertical heterostructures,for different thicknesses of Si NMs: 100 and 12 nm(figures 2(a) and (b)). The measured currents werenormalized as current densities by dividing them bythe area of overlap between the graphene and thetopmetal electrode. By sweeping the back gate voltage,the output characteristics could be continuouslymodulated between the off and on states. As back gatepotential changed, the current density monotonicallydecreased with increasing positive gate potential,demonstrating that the electrons were the majoritycharge carriers because lightly doped Si NMs wereused as the tunneling barrier in this vertical transistor.Near the diode turn-on regime, current can be modu-lated over several orders of magnitude by changing Vg,thereby allowing a switching operation with a largeIon/Ioff ratio. I–V curves for Vg=−50 V showed cur-rent rectification, although less rectification wasobserved for thinner devices; this will be further dis-cussed in the context of the results shown in figure 4.In the negative (reverse-bias) regime of source-drainvoltage (Vsd), the devices displayed conventional FET-

like device operation; the current tended to saturate athigh reverse bias voltages for thicker Si NM devices.On the other hand, in the forward bias region, the cur-rent did not saturate as Vbias increased.

Figures 2(c) and (d) show the transfer character-istics (Isd–Vg curves) for both devices studied, and forVsd values of 0.1, 0.25 and 0.5 V. The thicker deviceexhibited room-temperature on/off current ratios of103–104 for all Vsd values studied, which is sufficientfor typical logic device applications. It is also note-worthy that our graphene/Si NM vertical structurecan simultaneously achieve an on/off ratio of 104 anda high current density, substantially exceeding the on/off ratios in the range of 2–20 that have been reportedfor pure graphene transistors [25]. Because the currentin the on state is determined by the series resistance ofthe device rather than the resistance of the graphene/Si NM Schottky barrier, the on-state current densityis nearly the same for both devices. In contrast, theoff-state current density is significantly reduced forthicker devices owing to the high gate-induced barriermodulation, thereby increasing the on/off ratio forthicker devices. Such thickness dependence seems tobe a general behavior of this type of vertical FET

Figure 2.Room-temperature electrical properties of vertical transistors: (a, b) Isd–Vsd output characteristics of vertical transistors withSiNM thickness of (a) 100 nm and (b) 12 nm;measured current is normalized by the device area. (c, d) Isd–Vg transfer characteristicsof the devices at various biases Vsd, for SiNM thicknesses of (c) 100 nmand (d) 12 nm.

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[26, 27]. A higher on/off ratio was obtained for the100 nm-thick Si NM tunnelling barrier than for the12 nm-thick barrier. Ion/Ioff is thus determined by themodulation of the electric field across the junctions;more importantly, it can be optimized by varying thebarrier- defining parameters, thickness and workfunction of the metal, because these parameters deter-mine the band profiles for various bias conditions,which influence the device performance.

The band structure at the graphene/Si interfacecan be schematically illustrated as shown infigures 3(a)–(c), which describe the operation of thedevice. A gate electric field is applied between the sili-con back gate and the grounded top metal electrode.The key factor in device operation is the effectivemod-ulation of the graphene/Si NM barrier height and theFermi level (EF)near the graphene/SiNMcontact, dueto the limited density of states of graphene and its weakelectrostatic screening effect. When no gate or biasvoltage is applied, the Fermi levels of the graphene arelocated near the bottom of the Si NM valence band(figure 3(a)). The gate voltage Vg between the siliconsubstrate and the graphene layer changes the carrierconcentration in graphene, shifting the Fermi level byΔEF=±hνF√|η|. The sign of the Fermi level shift isdetermined by the polarity of the gate voltage. PositiveVg elevates the Fermi level of graphene, which causesband bending in the semiconductor and thus leads toan increase in the Schottky barrier (jb) at the gra-phene/Si NM interface (figure 3(b)). In this case,transport is dominated by the Schottky barrier at thegraphene/Si NM interface, and thus exhibits highresistance, corresponding to an off state. As a result, apositive gate voltage increases the Schottky barrierheight as well as the depletion width, suppressing car-rier transport across the vertical stack. In contrast,negative Vg lowers (shifts downward) the Fermi levelof the graphene, causing a decrease in jb at the gra-phene/Si NM interface as well as a decrease in thedepletion width of the Si NM layer (figure 3(c)). In thiscase, electrons can pass the Schottky barrier readily bymeans of thermionic emission or thermionic fieldemission processes; this enhances charge transport inthe vertical device, corresponding to an on state. Byvarying Vg to switch between the on and off states, thedevice can be operated as a vertical field-effect tunnel-ing transistor.

To further probe the charge transport through thegraphene/Si NM/metal vertical transistor, studies ofits temperature dependency were carried out. Currentdensity versus Vg was measured at various tempera-tures from 300 to 125 K at the fixed Vsd of +0.25 V(figures 4(a) and (b)). The current monotonicallydecreased with decreasing temperature for both cases;however, the J–Vg characteristics of the two samples ofdifferent thicknesses (t=12 and 100 nm) at varioustemperatures (T) had significant differences. Fort=12 nm (figure 4(b)), the thermal variation of J wasfound to be within one order of magnitude, and Ion/

Ioff remained almost constant throughout the tem-perature range from 125–300 K; this implies that thedominant contributor to total current was a tempera-ture-independent tunnelling component. In contrast,Joff for the thicker Si NM device (t=100 nm) wasdominated by thermal activation above 200 K, andIon/Ioff varied by two orders of magnitude over therange from 125–300 K. These variable-temperaturetransport measurements allow the Schottky barrierheights across the graphene/Si NM junction to bedetermined. According to thermionic emission the-ory, the diode saturation current is related to theSchottky barrier height by the following equation:

I AA Tq

k T

qV

k Texp exp 1 , 1b

B

b

B

2 ( )⎛⎝⎜

⎞⎠⎟

⎡⎣⎢

⎛⎝⎜

⎞⎠⎟

⎤⎦⎥*

fh

=-

-

where A is the area of the Schottky junction, A* is theeffective Richardson constant, q is the elementarycharge, kB is the Boltzmann constant, and T is thetemperature. fb can be calculated by investigatingthe temperature dependence of current in the reverse-bias saturation regime, where qVb k Texp 1 ;B[ ( ) ]h /thus saturation current can be considered indepen-dently of bias voltage, and can be simplified asI T q k Texpsat b B

2 ( )fµ - / [14]. The saturation cur-rent was determined from a logarithmic plot; ln(Isat/T2) is plotted against 1000/T for different gate biasvoltages in figures 4(c) and (d). From equation (1), theSchottky barrier height can be estimated from theslope of these curves as−jb/kB. The derived Schottkybarrier height shows a clear dependence on Vg as wellas on tunnelling thickness. At negative Vg, when thedevice is in an on state, the slopes of the curves are less,indicating the devices’ smaller potential barriers. Onthe other hand, at positive Vg, the slope of the curve ismuch larger for the t=100 nm device than for thet=12 nm device, suggesting a larger jb. This changein Schottky barrier height can be largely attributed tomodulation of the graphenework function. As the gatebias voltage changes from −50 to +50 V, the derivedSchottky barrier height also changes from 270 to55 meV as the Vg is increased, as shown in inset offigure 5(d). As gate voltage increased from −50 to50 V, jb increased substantially. We attributed thedrastic change in jb to the electric field effect-inducedFermi level change, ΔEF. Higher Δjb was obtainedfor the thicker Si NM, where Δjb=jb(on-state Vg)−jb(off-state Vg).

To further investigate the effects of Si NM thick-ness, we experimentally investigated a large numberof GSM devices of varying device sizes and Si NMthicknesses. Off-state (Vg=−50 V) and on-state(Vg=+50 V) current density data were collected; theon-state current density was nearly constant for all SiNM thicknesses (figure 5(a)). The overall on-state cur-rent density typically ranged from 101 to 102 A cm−2,with a weak dependence on Si NM thickness. Wealso fabricated graphene/Si NM/graphene Schottkybarrier (SB) devices to carry out control experiments;these devices yielded on-state currents about two

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2DMater. 2 (2015) 044006 TDas et al

orders of magnitude smaller than those of the gra-phene/Si NM/metal Schottky barrier devices, andhad lower on/off current ratios. The GSM structureminimized the top Schottky barrier height, thereby

reducing its modulation when a low-work-functionmetal was used. Thus, in this structure, charge trans-port is dominated by the bottom graphene/SiSchottky barrier height and width, which can be

Figure 3. Schematic of the transistor’s vertical architecture: (a)Band diagram corresponding to zeroVg and an applied Vg. (b)PositiveVg shifts the Fermi level of the two graphene layers down from the neutrality point, increasing the potential barrier and switching thetransistor off. (c)Negative Vg decreases the Schottky barrier height and increases the reverse current.

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2DMater. 2 (2015) 044006 TDas et al

effectively modulated by the back gate voltage to yieldhighly efficient injection and transport. Based on theon- and off-state current density data shown infigure 5(a), on/off current data were plotted; this plotshowed that the room-temperature on/off currentratios of the VFETs strongly depended on the Si NMthickness. The temperature dependence of the con-ductance was studied for graphene/Si NM/metaldevices of different Si NM thicknesses ranging from 8to 100 nm. A series of measurements were carried outto determine the amplitude of the barrier height mod-ulation,Δjb, versus changes in the thickness of the SiNM (figure 5(c)). The thickness dependence of theSchottky barrier height Δjb determined from Arrhe-nius plot and on-off ratio exhibits good coincidencewith figure 5(b). Figures 5(b) and (c) further confirmthat the modulation of the Schottky barrier height atthe graphene/SiNM interface plays a dominant role inthe switching operation of the vertical transistor. Ingeneral, it was found that the room-temperature on/off ratio of the vertical transistors exceeded threeorders of magnitude for a relatively thick Si NM(>70 nm), and gradually decreased to 10 when the Si

NM thickness was reduced below 10 nm. Reduced on/off ratios in thinner NMs have been reported pre-viously, and have been attributed to metal-inducedlowering of the Schottky barrier height [12]. This low-ering, which is also referred to as the Schottky effect,can contribute to the image force lowering and quan-tum capacitance of graphene. Both image force andquantum capacitance are inversely proportional tochannel length, which in this case corresponds to thethickness of the Si NM [28, 29]. With decreasing SiNM thickness, the entire channel becomes increas-ingly dominated by this effect, thereby reducing Δjband resulting in a smaller on/off ratio. The room tem-perature on/off ratio of >103 achieved in our deviceswas about two orders of magnitude smaller than theon/off ratio achieved in recently reported barristors[14]. This might be attributed to the presence of inter-face defects at the graphene/Si NM interface in ourdevices; if so, this could be improved by the use of clea-ner interfaces in future studies. Ideality factors weredetermined for all values of Si NM layer thickness(figure 5(d)). Deviation from ideal diode behaviormaybe attributed to graphene/Si NM interface defects,

Figure 4.Temperature dependency of the diode’s characteristics: (a, b) Semi-log plots of J–Vg characteristics of graphene/SiNM/Nidevices at various temperatures ranging from125 to 300 K atfixedVsd=+0.25 V, for SiNM thicknesses of (a) 100 nm and (b)12 nm. (c, d)Arrhenius plots of vertical FETs,measured in the (c) on and (d) off states.

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and also probably to the electrostatic screening effectof the top Si NM/metal contact due to the ultrathin Sichannel thickness (length). The ideality factor wasclose to unity for devices with Si NM thickness above26 nm, corresponding to near-ideal Schottky diodebehavior.

4. Conclusions

We have demonstrated integration of a verticaltunneling transistor by implementing ultrathin Sinanomembranes in GSM heterostructures; this canenable a new design for graphene-based verticaltransistors. The transport properties of the graphene/Si NM/metal vertical heterostructures were investi-gated over a wide range of Si NM thicknesses from 8 to100 nm. The devices showed a maximum on/offcurrent ratio (Ion/Ioff) of up to ∼10

3 with a currentdensity of 102 A cm−2 at room temperature forrelatively thick Si NM (>70 nm), thereby satisfying therequirements of high-performance logic applications.The change in the Schottky barrier height was higherfor thicker Si NMs (270 meV for a 100 nm Si NM,compared to 87 meV for a 12 nm Si NM), and it wasfound that the modulation of Schottky barrier height,Δjb, is a key factor to achieve larger current

modulation of the device. By using the device schemedeveloped herein, a variety of materials can beexplored and implemented in the future to enhancedevice performance.

Acknowledgments

This work was supported by the Global FrontierResearch Center for Advanced Soft Electronics(2014M3A6A5060933) through theNational ResearchFoundation of Korea (NRF), funded by theMinistry ofEducation, Science and Technology and the ResearchProgram of Korea Institute of Machinery & Materials(SC 1090).

Appendix.materials andmethods

The monolayer graphene was grown by CVD oncopper foil at 1035 °C and transferred onto a Si/SiO2substrate. Next, the graphene layer was patterned intostrips 25 μm wide and 100 μm long by optical photo-lithography and oxygen plasma etching to outlinedrain electrodes. The silicon substrate also served as aglobal back gate. In a parallel process, free-standingand isolated Si NMs were prepared from commercialSOI wafer, that is, Si (100 nm)/SiO2 (300 nm)/Si

Figure 5. Effects of Si NM tunneling layer thickness on the vertical transistor: (a, b) on/off current and on/off current ratio versus Si NM thickness. (c) Amplitude of barrier height modulation Δjb versus Si NM thickness. (d) Ideality factor h versus Si NM thickness, (d, inset) Schottky barrier heights under Vg modulation.

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(wafer) using polydimythylsiloxane (PDMS) stamp-ing. Details of the transfer process have been describedelsewhere [21]. Different batches of Si NMs wereprepared by two-stage oxidation (thermal and UV)varying the thickness of Si NMs in a range from 100-8 nm and transferred onto a bare Si chip coated with∼1 μm of polypropylene carbonate (PPC) (Sigma-Aldrich, CAS 25511-85-7). The transferred Si NMswere examined by optical microscopy and atomicforcemicroscopy (AFM) (Supplementary InformationS2). Before transfer onto graphene, native oxide on theexposed Si substrate was carefully removed by addi-tional wet etching followed by the passivation of the Sisurface with hydrogen treatment in a controlled atmo-sphere. Silicon can easily be oxidized by native oxygen,contaminating the interface. Before transfer, the SiNM surface was passivated by ozone in a UV ozonechamber. The presence of a thin ∼1 nm passivationlayer was confirmed by TEM; this layer is believed toserve as a surface protection layer. The PPC was thenmanually peeled from the Si substrate and placed on atransparent elastomer stamp. After that, the Si NMswere transferred onto pre-patterned graphene stripesby a dry transfer technique. The device was annealedin forming gas (5% H2, 95% Ar) for 1 h at 200 °C inorder to improve the interface properties. By usingelectron-beam lithography and thermal evaporation, aNi/Au (20/30 nm) metal electrode was fabricated ontop of the Si NMs to overlap with the bottomgraphene.

The cross-sectional TEM sample was preparedusing focused ion beammilling and characterized by aJEM-200F TEM operating at 300 kV. Tapping-modeAFMmeasurement was done by an XE-100 (Park Sys-tems). The I-V characteristics of the graphene-basedVFETs were measured by a Keithley 4200 SCS para-meter analyzer as a function of gate voltage at bothroom temperature and low temperature (300-125 K)in aN2 atmosphere under high vacuum.

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http://dx.doi.org/10.1063/1.4795542http://dx.doi.org/10.1063/1.4795542

1. Introduction2. Experimental methods3. Results and discussion4. ConclusionsAcknowledgmentsAppendix.References