6.111 Fall 2007 Lecture 11, Slide 1
1. Operational Amplifiers: an Introduction
• Typically very high inputresistance ~ 300KΩ
• High DC gain (~105)• Output resistance ~75Ω
DC Model
inout VfaV != )(
a(f)
f10Hz
105 -20dB/decade
LM741 Pinout+10 to +15V
-10 to -15V
idva ⋅idv
inR outR+
−outv
6.111 Fall 2007 Lecture 11, Slide 2
The Inside of a 741 OpAmpDifferentialInput Stage
AdditionalGain Stage Output Stage
Current Sourcefor biasing
Bipolar versionhas small inputBias current
MOS OpAmpshave ~ 0 input current
Gain is Sensitive to Operating Condition (e.g., Device, Temperature, Power supply voltage, etc.)
Output devicesprovides largedrive current
6.111 Fall 2007 Lecture 11, Slide 3
Simple Model for an OpAmp
+
-
i+ ~ 0
i- ~ 0+-
+-
vidvout
vout
vid
VCC = 10V
-VCC = -10V
ε = 100µV-100µV
Reasonable approximation
+
-vid +- avid
+
-vout
Linear Mode
If -VCC < vout < VCC
+
-vid -VCC
+
-vout
Negative Saturation
vid < - ε
-++
-vid
+
-vout
Positive Saturation
vid > ε
-+ +VCC
-VCC
VCC
Very small input range for “open loop” configuration
6.111 Fall 2007 Lecture 11, Slide 4
The Power of (Negative) Feedback
inv outv1R 2R
-+-
+vid +- avid
+
-voutinv
R2
-+
R1
0
21
=+
++
R
vv
R
vvidoutidin
a
vv
out
id= !
"
#$%
&++'=
2211
11
RR
a
Ra
v
R
voutin
( )( )1
11
2
21
2 >>!"++
!= aifR
R
RRa
aR
v
v
in
out
Overall (closed loop) gain does not depend on open loop gain Trade gain for robustness Easier analysis approach: “virtual short circuit approach”
v+ = v- = 0 if OpAmp is linear
+-
6.111 Fall 2007 Lecture 11, Slide 5
Basic OpAmp CircuitsVoltage Follower (buffer)
inv
outv
2R
1R
inR
RR
outvv
1
21+
!
+
"
Non-inverting
invoutv
1invoutv
2inv
1R
1R
2R
2R
( )121
2
ininRR
out vvv −≈
Differential Inputinout vv ≈
invoutv
R C
∫ ∞−−≈t
inRCout dtvv 1
Integrator
+
-
6.111 Fall 2007 Lecture 11, Slide 6
OpAmp as a ComparatorAnalog Comparator: Is V+ > V- ? The Output is a DIGITAL signal
LM311 uses asingle supplyvoltage
6.111 Fall 2007 Lecture 11, Slide 7
2. Data Conversion: Noise
• Quantization noise exists evenwith ideal A/D and D/Aconverters. SNR improves 6dBwith each additional bit
A/D D/A
digital
code
inv
Quantization
noise
+
!
00
01
10
11
04refV
2refV
43 refV
Analog Input
Bina
ry O
utpu
t
refV
A/D Conversion
inv
noisev
LSB
00 01 10 110
4
refV
2
refV
4
3 refV
Binary code
An
alo
g O
utp
ut
4refV
2refV
43 refV
refV
D/A Conversion
6.111 Fall 2007 Lecture 11, Slide 8
Non-idealities in Data Conversion
Binary code
Anal
o g
Ideal
Offseterror
Offset – a constant voltage offset that appearsat the output when the digital input is 0
Binary code
Anal
o g
Ideal
Gainerror
Gain error – deviation of slope from ideal valueof 1
Binary code
Anal
og
Ideal
Integralnonlinearity
Integral Nonlinearity – maximum deviation fromthe ideal analog output voltage
Differential nonlinearity – the largest incrementin analog output for a 1-bit change
Binary code
Anal
og Ideal
Non-monoticity
6.111 Fall 2007 Lecture 11, Slide 9
3. Digital to Analog• Common metrics:
• Conversion rate – DC to ~500 MHz (video)• # bits – up to ~24• Voltage reference source (internal / external; stability)• Output drive (unipolar / bipolar / current) & settling time• Interface – parallel / serial• Power dissipation
• Common applications:• Real world control (motors, lights)• Video signal generation• Audio / RF “direct digital synthesis”• Telecommunications (light modulation)• Scientific & Medical (ultrasound, …)
6.111 Fall 2007 Lecture 11, Slide 10
R-2R Ladder DAC Architecture
Note that the driving point impedance (resistance) is the samefor each cell.
• R-2R Ladder achieves large current division ratios with only tworesistor values
-1
6.111 Fall 2007 Lecture 11, Slide 11
Labkit: ADV7125 Triple Out Video DAC
• Three 8-bit DACs• Single Supply Op.: 3.3 to 5V• Internal bandgap voltage ref• Output: 2-26 mA• 330 MSPS (million samples per
second)• Simple edge-triggered latch
based interface
6.111 Fall 2007 Lecture 11, Slide 12
Glitching and Thermometer D/A• Glitching is caused when
switching times in a D/A are notsynchronized
• Example: Output changes from011 to 100 – MSB switch isdelayed
100011!outv
t
0TI
R
outv
( )210 TTTIRvout ++−=
I I1T 2T
• Filtering reduces glitch butincreases the D/A settling time
• One solution is a thermometercode D/A – requires 2N – 1switches but no ratioed currents
ThermometerBinary
11001
11111
10010
00000
ThermometerBinary
11001
11111
10010
00000
6.111 Fall 2007 Lecture 11, Slide 13
4. Analog to Digital
• Common metrics:• Conversion rate – DC to ~100 MHz• # bits – up to ~20• Input range – unipolar / bipolar• Interface – parallel / serial• Type: successive approximation, sigma-delta, flash
• Common applications:• Real world sensing (position, speed, force, temperature, …)• Video signal digitization• Audio / RF recording & receiving• Telecommunications (light demodulation)• Scientific & Medical
6.111 Fall 2007 Lecture 11, Slide 14
Successive-Approximation A/D
Example: 3-bit A/D conversion, 2 LSB < Vin < 3 LSB
Vref
0.5Vref
0
Vin
t = 0 t = 1 t = 2
code = 100 code = 010 code = 011D/A
output
0
1
Comparator output
010
t
t
D/A converters are typically compact and easier to design. Why notA/D convert using a D/A converter and a comparator? DAC generates analog voltage which is compared to the input voltage If DAC voltage > input voltage then set that bit; otherwise, resetthat bit This type of ADC takes a fixed amount of time proportional to thebit lengthVin code
D/A
Comparator
out
C+ !
6.111 Fall 2007 Lecture 11, Slide 15
Successive-Approximation A/D
Serial conversion takes a time equal to N (tD/A + tcomp)
SuccessiveApproximation
Generator
Control
Done
Go
-
+Sample/Hold
D/AConverter
vin
N
Data
6.111 Fall 2007 Lecture 11, Slide 16
• Digitize differential signal:
Sigma Delta ADC
integrator
1-bit DAC
+ +- Bit stream
-+
Analoginput
1-bit ADC
LPF DecimatorBit stream samples
REFV±
REFINREFVVV <<!
•Sigma Delta modulator runs at many times Nyquist frequency•Average of bit stream (1=VREF, 0=-VREF) gives voltage•Integrator is high-pass filter for noise, most of which is then removed by low-pass filter ⇒ excellent SNR (> 100dB)
6.111 Fall 2007 Lecture 11, Slide 17
Sigma Delta ADC
• A simple ADC:R
C
Vref Controller(FPGA)
Vin
RVin
Controller(FPGA)
C
• Poor Man’s ADC:
6.111 Fall 2007 Lecture 11, Slide 18
Flash A/D Converter
• Brute-force A/D conversion• Simultaneously compare the
analog value with everypossible reference value
• Fastest method of A/Dconversion
• Size scales exponentiallywith precision(requires 2N comparators)
+
−
+
−
+
−
R
R
refV inv
0b1b
Ther
mom
eter
to b
inar
y
ComparatorsR
R
6.111 Fall 2007 Lecture 11, Slide 19
High Performance Converters:Use Pipelining and Parallelism!
Sample/
Hold
!
+
Amplifier1-bit
A/D
Converter
D/A
Converter 2
Sample/
Hold
!
+
Amplifier1-bit
A/D
Converter
D/A
Converter 2
…
Pipelining (used in video rate, RF basestations, etc.)
Parallelism (use many slower A/D’s in parallelto build very high speed A/D converters)
[ISSCC 2003],Poulton et. al.
20Gsample/sec,8-bit ADCfrom Agilent Labs
6.111 Fall 2007 Lecture 11, Slide 20
5. Interfacing to FPGA’s
• Parallel (memory mapped peripheral)Typical example: AD670 ADC
Read Result
Indicates result ready
Start Conversion
busy
6.111 Fall 2007 Lecture 11, Slide 21
Simple A/D Interface FSM
Data[7:0]
STATUS
CSCE
AD670
cs_b
R/Wr_w_b
FSM
clk
reset
sample
DQ
dataavail
status
Status should be synchronized: why?
Courtesy of James Oey and Cemal Akcaba
6.111 Fall 2007 Lecture 11, Slide 22
Example: Digital Potentiometer
• AD5246 “128-position digital resistor
• Writing potentiometer setting:
2mm x 2.1mmpackage!
• I2C Serial bus: one master, multiple slave devices
Master(FPGA)
Clock (SCL)
Data (SDA)
6.111 Fall 2007 Lecture 11, Slide 23
Example: Digital Potentiometer
• Read potentiometer setting:
• Serial protocols: I2C, SPI, “one-wire”
# I2C interfacemodule i2c(clk,rdata,rd,wdata,wr,scl,sda); input clk,rd,wr; input [7:0] wdata; output [7:0] rdata; output scl; inout sda; reg dir,sdout; assign sda = dir ? 1’bZ : sdout; . . .endmodule
•Verilog
6.111 Fall 2007 Lecture 11, Slide 24
Summary
• OpAmps:– Basic elements of most conversion circuits– Gain determined by ratios of resistances
• DAC’s:– R2R ladder ; fast operation
• ADC’s:– Successive Approximation, sigma-delta, flash– Be sure to synchronize signals
• Analog jellybean parts:– Digital potentiometers, I2C thermometers,…– Use INOUT for bidirectional lines in verilog
inv
outv
1R
2R
-+
+
-
integrator
DAC
+ +
-
Digitaloutput
-+
Analoginput
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