8/3/2019 Verilog for Sequential Circuits
1/23
Verilog forSequentialCircuits
8/3/2019 Verilog for Sequential Circuits
2/23
Verilo for Se uential Circuits
Sequential circuits are modeled in an alwaysblock
Example of an implied memoryelement
The gated D latch
Verilog assumes the value of Qmust be maintained if Clk is 0 andtherefore synthesizes a latch
8/3/2019 Verilog for Sequential Circuits
3/23
Verilo for D Fli -Flo
Sensitivity list needs to specify clock edge, not just
change in level Can specify: posedge or negedge
Verilog will use flip-flops to synthesizecircuits that are edge-triggered
8/3/2019 Verilog for Sequential Circuits
4/23
Verilo for T and JK Fli -Flo s
Negative edge triggered versions
Also provides complemented outputs
8/3/2019 Verilog for Sequential Circuits
5/23
Verilo Exam le
=
x3
D Q
Q
gx1
x2
D Q f
Clock Q
8/3/2019 Verilog for Sequential Circuits
6/23
Verilo Exam le: Reversed Order
Order matters inside an always block!
D Q
Q
gx3
x1
Clock Q
x2
8/3/2019 Verilog for Sequential Circuits
7/23
Blockin Assi nments
The order of statements inside an always block can
affect the synthesized design All previous examples use blocking assignments
order in which they are written
D QD Q1
Q
2
treated as Q2 = D since Q1 = D
8/3/2019 Verilog for Sequential Circuits
8/23
Non-Blockin Assi nments
What if you wanted a cascaded design for the
previous example? The assignment to Q2 should be from the previous Q1
clock edge
The LHS of a non-blocking assignment is updated after allRHS values for all assi nments have been evaluated
D Q
QClock
D Q
Q
D
non-blocking assignment
8/3/2019 Verilog for Sequential Circuits
9/23
Non-Blockin Exam le
Compare this to the earlier exampleusing blocking assignments
D Q
Q
gx3
D fx1
Clock Q
x2
8/3/2019 Verilog for Sequential Circuits
10/23
8/3/2019 Verilog for Sequential Circuits
11/23
Addin As nchronous Clear
The sensitivity list cannot mix edge triggered and
level sensitive events Must make resetedge-triggered, but on a different edge
8/3/2019 Verilog for Sequential Circuits
12/23
S nchronous Clear
The only change is in the sensitivity list
ResetN overrides the input
8/3/2019 Verilog for Sequential Circuits
13/23
Verilo for N-Bit Re ister
8/3/2019 Verilog for Sequential Circuits
14/23
Verilo for N-Bit Re ister With Load
Add a load enable input
8/3/2019 Verilog for Sequential Circuits
15/23
Verilo for 4-Bit Shift Re ister
One technique: build a Q3 Q2 Q1 Q0
Parallel output
simple 2X1 MUXcontrolled D flip-flop
D QQ
D QQ
D QQ
D QQ
ClockShift/LoadSerial npu
Provide arallel access includinload) and shift right
8/3/2019 Verilog for Sequential Circuits
16/23
4-Bit Shift Re ister: Continued
behavioral and structural styles
8/3/2019 Verilog for Sequential Circuits
17/23
N-Bit Shift Re ister: Behavioral St le
8/3/2019 Verilog for Sequential Circuits
18/23
N-Bit U Counter
Provide an n-bit up counter with asynchronous clearand an enable control
8/3/2019 Verilog for Sequential Circuits
19/23
N-Bit U Counter With Load
Provide an n-bit up counter with asynchronous clear,an enable control, and parallel load
8/3/2019 Verilog for Sequential Circuits
20/23
N-Bit U /Down Counter With Load
8/3/2019 Verilog for Sequential Circuits
21/23
Alternate Version of U/D Counter
blocking assignments are executede ore non- oc ng ones
8/3/2019 Verilog for Sequential Circuits
22/23
Good Codin St le
As a matter of good coding style
Do not mix blocking and non-blocking assignments in thesame always block
It may work, but you may confuse yourself!
Use separate always blocks when you need both types
Repeating earlier rules
Use blocking assignments for combinational logic
Use non-blocking assignments for sequential logic, andlatches
8/3/2019 Verilog for Sequential Circuits
23/23
Best Version of U/D Counter
This style separatesblockin and non-blockin
assignments into separatealways blocks
Top Related