Thomas J. Watson Research Center
© 2006 IBM Corporation
Statistical Timing in a Practical65 nm Robust Design Flow
Chandu Visweswariah
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The power of statistical formulas
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Acknowledgements
� The extended statistical timing, statistical optimization, timing support and timing methodology teams at IBM Yorktown, Fishkill, Burlington, Poughkeepsie, Rochester and Waltham
Caveat
� This presentation is mostly ASIC-focused, although microprocessor design issues will be mentioned(time permitting)
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Outline
� Yield loss mechanisms and the tradeoffs involved
� What is robust design?
� A timing closure methodology based on statistical timing
� Myths about statistical timing
� Interesting challenges
– early/late splits and CPPR
– at-speed test
– metrics for optimization
– delay modeling for 45 nm
– hierarchical statistical timing
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Catastrophic vs. parametric yield loss
Dummy fill Dummy fill
Source: NEC0%
20%
40%
60%
80%
100%
350nm 250nm 180nm 130nm 90nm
Yie
ld
Parametric (design-based)Parametric (design-based)
Lithography BasedLithography Based
Defect BasedDefect Based
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Increasing and inevitable parametric variability
*D. J. Frank et al, Symp. VLSI Tech., 1999
Litho-induced variability Random dopant effects* Oxide thickness
Interconnect CMP and RIE effects
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Normalized metal resistance data over 3 months
1.0
3.0
1.5
2.0
2.5
� Wafer means change over time
� Values are “out-of-spec,” need to yield within WAC limit
We would like toretain these wafers
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Manufacturing for predictable performance
� Cp and Cpk (Process Capability Indices) measure manufacturing predictability
� Manufacturing typically (but not always) outperforms spec. limits
Lower spec. limit Upper spec. limitNominal spec.
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Normalized cumulative statistics1.0
2.5
1.5
2.0
� Distributions are not Gaussian (but usually close)
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Ring oscillator performance distributionsp
ec
Slo
we
r
Percentage of chips� Color coding is by wafer
� Hardware is faster/tighter than predictions
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Normalized metal resistance across manufacturing lines
1.00.920.840.760.680.600.520.440.368 0.9280.7680.6880.6080.5280.448 0.848
� Designs must yield at multiple fabs.
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Normalized single-level capacitance distribution
0
50
100
150
200
2501.0
1.0
53
1.1
05
1.1
58
1.2
11
1.2
65
1.3
18
1.3
71
1.4
23
1.4
76
1.5
29
1.5
82
1.6
35
1.6
88
More
� Variability is enormous!
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Any performance left in worst-case design?
90 nm
65 nm
45 nm
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What do we do with all this variability?
As we know, There are known knowns.
There are things we know we know.
We also know There are known unknowns.
That is to say We know there are some things
We do not know.
But there are also unknown unknowns, The ones we don't know
We don't know.
Donald H. Rumsfeld1
1Dept. of Defense news briefing, 2/12/02, linebreaks mine
Knownknowns
Knownunknowns
Unknownunknowns
Statisticaltiming and
power analysis
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L
L
+∆∂
∂+∆
∂
∂+
+∆∂
∂+∆
∂
∂+
=
2
2
2
2
2
2
),(
yy
py
y
p
xx
px
x
p
meanyxP
Robust circuit design
� Its the sensitivities, stupid!
Fir
st
ord
er m
od
el
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Delay modeling Fast chip vs. slow chip
Chip means
Can get across-parameter RSS relief
SystematicACV
Can get space-dependent relief
RandomACV
Can get down-a-path RSS relief
Early Late Early Late
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Model-to-hardware correlation
Mean RO delay
RO
dela
y
Fast chip Slow chip
Late
Earl
y
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Bounding distributions1.0
2.5
1.5
2.0
� Bounding distributions provide protection from various sins!
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Statistical-timing-based flow
� Conduct statistical timing with correlations
– predict timing slacks in “canonical” form parameterized by the sources of variation
� “Project” flop slacks to worst corner; if positive, we are safe
� Get “debits” and “credits”
– mixed-mode projection
– spatial
– coupling noise
– independently random
� Check sensitivities
– alternative statement of Murphy’s law: “Variability exacerbates poor design!”
– encourage “balanced” or “robust” design
� Check single-corner timing with all bells and whistles
� Optimization and fix-up
– use incremental statistical timing
– various diagnostics available
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Myths about statistical timing
� “The main reason for statistical timing is within-die variations” … “Variability is dominated by within-die variations” … “The main frequency limiter is within-die variations”
� Random dopants are the only truly statistical phenomena
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Courtesy Anne Gattiker, IBM
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Courtesy Anne Gattiker, IBM
Across-wafer variations
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Interesting challenges: early/late splits and CPPR
LL1 LL2 CLLL3
late data
Sam
e b
uffer
has
diff
ere
nt dela
ys o
n e
arly/
late
path
s
early
clo
ck
Undue pessimism
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Interesting challenges: at-speed testing
Chip Under Test
PLL Clock control
Logic
RefClk
StartTest
ClkFrom tester:
Scan & Test Clocks
Test Data
[Courtesy Gary Grise]
Clk
Scan Clock
PLL Output
Last Scan-Load Cycle At-Speed Test Scan Unload Cycles
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Interesting challenges: at-speed testing
� Each point in the process space can have a unique critical path
� How to come up with a set of test vectors that testsfor parametric variations in all parts of the process space?
� How to measure coverage thereof?
� How to test against workload-related defects?
� How to test against fatigue-related defects?
Critical
Critical
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Interesting challenges: metrics for optimization
� Slack is lacking
– different critical paths in different parts of the process space
– slack is a distribution
– slack does not give robustness information
– relative ordering of paths
• slack does not give correlation information
Other open problems
� Delay+power+noise variational modeling for 45 nm
� Robust optimization, fix-up
� Hierarchical robust design
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Conclusions
� Must protect against parametric variability
– high dimensionality, hence the need for statistical timing
– hence the need for robust design
– hence the need to check sensitivities
– hence the need for statistical timing!
� IBM has adopted a statistical-timing-based robust design flow for 65 nm ASICs
� Many open and interesting challenges remain
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