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SPI
1
Serial Peripheral Interface
Some registers parameters are only for 55800
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SPI
2
SPI FeaturesMaster/Slave- Supports up to 15 external devices
Supports SPI modes 0 1 2 ! "- #ll com$inations of cloc% p&ase and polarity
Programma$le'- 8 to 1( $it )ata *engt&- )elays $et+een c&ip selects- )elays $et+een consecutive transfers
- )elays $et+een cloc% and data per c&ip selectSelecta$le Mode ,ault )etection,ixed or aria$le perip&eral selectionPerip&eral )ata .ontroller P).- .&ained uffer support
*ocal *oop $ac% in Master mode
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SPI
"
SPI Block Diagram
PM.
)I-
SPI Interface
M.
M. /"2
P).
#P
PI3
SP.
MIS3
M3SI
4P.S0/4SS
4P.S1
4P.S2
4P.S"
SPI Interrupt
#P ridge
#S
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SPI
DependenciesPM. &as to $e programmed 1 st for SPI to +or%PI3 .ontroller &as to $e programmed for t&e pins to $e&ave asintendedSPI Perip&eral Inputs 6see7 t&e state of t&e pad
,or example'- 9se t&e SPI as a transmitter only- Program t&e PI3 controller pins for SP. and M3SI to $e outputs- Program t&e PI3 controller pin for MIS3 to $e a :PI3
; o+ever if t&e SPI sees a 0 on 4SS PI3 line a Mode ,ault can $e generated
8/12/2019 SPI Slides
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SPI
5
Master Mode Clock Generation
S. ? is 0 on reset 0 leads to un-predicta$le results- Set to somet&ing ot&er t&an 0 $efore 1 st transfer- @ac& .&ip Select can &ave its o+n $aud rate
; ,)I is t&e same for all c&ip selects
M. /"2 1
0M.
,)I-
aud ?ate :enerator SP.
SPIA.S?0 "
S. ?15 8
SP. B M. / 4 C S. ?
B 1 to 255
SPIAM?"
01
1"2
,)I- 4
SPI .*3.
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8/12/2019 SPI Slides
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SPI
F
Master Mode Shift Register
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SPI
8
Mode Fault
Mode ,ault occurs +&en t&e SPI is a master and anot&er master &asasserted 4P.S0/4SS lo+
- 4P.S0/4SS is normally configured as an open drain- #dd an external pull-up to 4P.S0/4SS to prevent spurious mode faults
@na$led $y defaultSPI perip&eral gets disa$led +&en fault occurs
1 ?ead SPIAS? to clear M3), $it2 ?e-ena$le SPI perip&eral t&roug& SPIAM? SPI@4 $it
4P.S0
MS
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SPI
H
Data Transfer Dela s
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SPI
10
Transfer Dela s)elay et+een .&ip Selects D!"BCS- 9se to accommodate SPI devices +it& long float times- )elay B of M. periods if ,)I B 0 or of M. periods J "2 if ,)I B 1- If )*G .S K ( its set to ( to guarantee a minimum delay
; 3r ( J "2 M. periods if ,)I B 1
4P.S0
4P.S1
SP.
D!"BCS )*G S )*G .< )*G .
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