SOC ATE System Design for TFx
Jin-Soo Ko
November 16, 2011
2011 Test Technology
Workshop
20011 Test Technology Workshop November 16, 2011 James J. Ko
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Performance Analog & Mixed Signal
Analog ASIC
Semiconductor Device SegmentsD
igit
al P
erf
orm
an
ce
High Speed Memory
Low Cost
Consumer
Low Speed Memory
Memory
Complex SOC
PC
(MPU,GPU)
Mixed Signal
(A/V, STB, ODD)
Cellular
(RF, Baseband)
DRAM, MCP, FLASH
MCU, LDI, Imager
Auto, Telecom
Power, Linear, Sensors, Discrete
GDDR5, DDR3
20011 Test Technology Workshop November 16, 2011 James J. Ko
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SOC Device Trends
Mobile Smart phone, Tablet PC feature and devices-more internet connection and cloud computing
-needs complex RF, Digital, PMIC chips
Easy to use by adding more human interface H/W and S/W
-Wide rage of new devices with Sensors
20011 Test Technology Workshop November 16, 2011 James J. Ko
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Device Architecture Trends:
• Re-use of complex and 3rd party IP
• Asynchronous core interfaces
• Independent PLLs within IP cores
SOC Device Design Trends and Architecture
Integrated Mobile Device
CPU
DRAM
I/F
Flash
I/F
JTAG
I/F
USB
I/F
DSPBB
Proc
Power Mgmt
FunctionsAudio / BB
Functions GPS
3G RF
WiFi
FM/TV
Chaotic process of IC Design:IP-based SoC designs have introduced new levels of complexity to the
IC development process- a multitude of design data from a variety of sources
- constantly changing design, requirements and process
20011 Test Technology Workshop November 16, 2011 James J. Ko
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Complex SoC Device Feature & Test Demand
Demand for increasing test capability
• More data bandwidth 3G, LTE and LTE Advanced
• High speed interfaces Digital data rates
• Longer Battery Life Power management
• “More” connected More radio interfaces (GPS, WiFi, Bluetooth, FM, NFC)
Continuous cost reduction Higher throughput
2.5G PCI Express compliance pattern
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Complex SOC Device Trends and Test
System in Package:
Source: Aspen Technologies
Advanced Packaging (TSV, WL-BGA)Single Insertion Test
KGD quality requirements
Critical device quality requirementsMore extensive testing
End-to-End functional test - “RF to bits”
Many RF and digital interface standards
Short product lifetimesRapid production ramps
Shorten test development cycles
Large volumes, Significant cost pressuresIncreasing Multi-Site counts
Innovations for increase throughput
Independent
16 site design
North
Independent
16 site design
South
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Continuous COT reduction for Customers
Increased throughput:• Increased site count w/higher density instruments & MUX modules
• Improved single site test time & parallel test efficiency w/features
Increased throughput and yield with New test strategies:• Concurrent Test for reduced test times
• Protocol Aware for reduced test time and retest
Improve Customer’s Time to Market
Improve program development & debug time:• Test IP reuse & collaborative development
• Concurrent Test development model and tools
• Evolve from pattern to transaction programming with Protocol Aware
IG-XL API’s to interface the tester w/design & production
environments
SOC ATE System Development Objectives
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Multi-site capability is the key strategy to achieve low cost of test in SoC business
4-site codec in 2001
8-site CDP/DVDP in 2004
16-site Mobile A/V processor in 2007
32-site Mobile A/V processor in 2009
16-site Mobile A/V processor in 2011 and after
Gen. 3
World’s first 8-site
CD, DVD Player Processor
SOC test solution
World’s first 16-site
Mobile A/V Processor
SOC test solution
2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011
2 or 4-site 16-site 32-site 16 to 64-site?
Gen. 3-2Gen. 2
4-site Optical Disk
Drive SOC test
solution
8-site
World’s first 32-site
Mobile A/V Processor
SOC test solution
Gen. 3-3
64-site SOC device test solution
Using new high density (x2 ~ x4)
UltraFLEX future option
or
8 to 16 sites test solution for over
1000 pin devices
Gen. 3-4
SOC Multi-site Test for Reduction in COT
20011 Test Technology Workshop November 16, 2011 James J. Ko
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More High Density Wide-Bandwidth Options for Reduction in COT
SB6G: 8 Lanes 6.4Gbps Serial
HSD1000: 64 Ch 1Gbps
UltraPin800: 128 Ch 800Mbps
BBAC: 2 Src / 2 Meas, 15MHz
TurboAC: 2 Src / 2 Meas, 15MHz+
VHFAC: 2 Src / 2 Meas, 100MHz+
DC30: 20 Ch 30V / 200mA
DC75: 4 Ch 75V / 2A
UltraSerial10G: 20 Lanes 10Gbps Serial (PA)
UltraPin4000: 80/40 Ch 4Gbps
UltraPin1600: 256 Ch 1.6Gbps (PA)
UltraPAC80: 8 Src / 8 Meas, 80MHz+
UltraVI80: 80 Ch, 7V / 1A (4A merged)
Current 2010 2011
Increased Performance for future devices
Increased throughput for higher site count with increased channel density
Compatible
Transitions
Digital Option
AC Option
DC Option
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Multi-Site Test and Parallel Test Efficiency
• DIB (Mother) board- High speed Digital and precision AC
connections
- Move AC applications to test head
• Daughter board- DC test application circuit and relays
- 1 DC Block supports 4 sites testing
- 8 copies of the DC Block for 32 sites
• AC Expansion board- Provide Common AC applications on
test head for the multi-site AC testing
• Option assignment - North16 & South16 sites identical
DIB design for testing independently
• Symmetrical site to site circuit
design- Improve the site to site correlation
Daughter Board
(8 DC Blocks)
DIB Board
(AC and Digital)
Independent
16 site
design
North
Independent
16 site
design
South
ACEX
ACEX
Bloc
k ABloc
k B
Bloc
k C
Bloc
k ABloc
k B
Bloc
k C
Bloc
k ABloc
k B
Bloc
k C
Bloc
k ABloc
k B
Bloc
k C
Tester
Resources Tester
Resources
Tester
Resources
Computer
DUT
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A B
C DE F
Serial Test Flow
Tests
Core A
Tests
Core B
Tests
Core C
Tests
Core D
Tests
Core E
Tests
Core F
Test
Time
Setup
Full Functional
Test
Tests
Core ATests
Core BTests
Core CTests
Core D
Tests
Core E
Setup
Tests
Core F
Test
Time
Full Functional
Test
Concurrent Test Flow
Concurrent Test Vision
Simple creation of a Concurrent test flow
contained in the Serial test program
No changes to the tests code for serial
flow or concurrent flow
Support Multiple levels of concurrency
with distributed instrument control
including Sync-Link (PSets/Signals)
Full support for Multi-site test and optimal
Parallel Test Efficiency
Two Flows, One Program
Priorities:
#1) Minimize Development Time
#2) Optimize Concurrent Test Efficiency
Vision for Concurrent Test
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A B
C DE F
Tests
Core A
Tests
Core D
Tests
Core B
Tests
Core C
Tests
Core F
Tests
Core E
Collaborative
Development
Step #1 Step #3Step #2Step #0
System
Configuration
Resources
Required per
Core
(DUT & Tester)
Resource
Conflict
Checker
Blocks can
Operate
Concurrently
Function_Names
Variable_Names
DIB Design
Concurrent Flow
Common Pin Management
Etc.
Test Program Resource “Conductor”
Concurrent
Core
Operation
Planning
DIB Design
Checklist
Tests
Core ATests
Core BTests
Core CTests
Core D
Tests
Core E
Initial
Tests
Core F
Test
Time
Full Functional
Test
Concurrent Test FlowSerial Test Flow
Tests
Core A
Tests
Core B
Tests
Core C
Tests
Core D
Tests
Core E
Tests
Core F
Test
Time
Initial
Full Functional
Test
Concurrent Test Program Development Process
20011 Test Technology Workshop November 16, 2011 James J. Ko
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Tests
Block ATests
Block BTests
Block CTests
Block D
Tests
Block E
Initial
Tests
Block F
Test
Time
Full Functional
Test
Concurrent Test FlowSerial Test Flow
Tests
Block A
Tests
Block B
Tests
Block C
Tests
Block D
Tests
Block E
Tests
Block F
Test
Time
Initial
Full Functional
Test
Development Challenges
• Common bus/pins
• Shared test resources
• Flow manipulation
• Multi-site implementation
• Adaptive test & Retest
• Debug tools
Same Test code for Serial and Concurrent Flows
Software Environment:CTExec Software
20011 Test Technology Workshop November 16, 2011 James J. Ko
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Tests
Block ATests
Block BTests
Block CTests
Block D
Tests
Block E
Initial
Tests
Block F
Test
Time
Full Functional
Test
Concurrent Test FlowSerial Test Flow
Tests
Block A
Tests
Block B
Tests
Block C
Tests
Block D
Tests
Block E
Tests
Block F
Test
Time
Initial
Full Functional
Test
Development Challenges
• Common bus/pins
• Shared test resources
• Flow manipulation
• Multi-site implementation
• Adaptive test & Retest
• Debug tools
Software Environment:TimeLines Viewer
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What is Protocol Aware Test?
Stored Response ATE Protocol Level ATE
Execute fixed pass/fail vectors Interact with DUT using standard protocols
(PCI-E, I2C, USB, LTE Advanced, etc)
Slave DUT to tester Adapt tester to DUT
Convert Design Information to Tester Language Use RTL level commands directly on tester
Integrated Mobile Device
CPU
Mem
I/FDRAM Emulator
JTAG AnalyzerJTAG
I/F
USB
I/FUSB Signal Analyzer
DSPBB
Proc
Power Mgmt
Functions
DC Test
Resources
Audio / BB
Functions
AC Test
Resources
3G
WiFi
Modulated RF data
generation/analyzer
Modulated RF data
generation/analyzer
Protocol Level
ATE
Protocol Synchronization & Communication
20011 Test Technology Workshop November 16, 2011 James J. Ko
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• Limited Protocol Aware ATE capability is available today
• A first generation Protocol Aware Instrument is the UltraFLEX SB6G
– Designed for at-speed test of High Speed Serial buses like PCI Express and SATA
– SB6G can recognize, manipulate, and compare 8b/10b encoded DUT output data
6.4Gb/s Data Rate
Clock
Data
Recovery
10 bit
Align
20 bit
Match
Disparity &
Symbol Map
RAM
SB6G Timing and Data Alignment Compare
Vector Data
Capture for
Out-of Order
Data Compare
Compare PRBS
Auto-seed
DUT output:
8b/10b encoded
data @ up to
6.4Gbps
Time align
to incoming
data
Data align
to specific
8b/10b
Symbol
Boundary
Data manipulation
- Ignore Idles
- Map +/- disparity
- Re-map symbols
Data align to
a specific two
symbol
sequence
- At-speed compare
with stored pattern
- At-speed compare
with PRBS pattern
- Capture for later
compare with
Out-of-Order data
DUT Output Data
First Generation Protocol Aware ATE
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• PA Architecture is Integrated into Standard Digital Functionality
- PA or Standard Digital Programmable on a Pin by Pin basis
• Protocol implementation with FPGAs in datapath to minimize latency and support field upgrades
• Architecture supports configurable protocols to enable users to customize interfaces
• Architecture will support dedicated protocols to enable use of 3rd party IP
• FPGA Architecture Allows Flexibility
- Upgrades Done in Field with Firmware/Software
- Roadmap Updates Over Time
Protocol Level ATE Architecture
TT
Timing
Pin Electronics
PEHost
Computer
FPGA Based
Protocol
Engines
DUT
“stored
response”
digital
DSSC
Logic
Patgen
Transaction
Memory
Select between normal
PE operation and
Protocol Aware
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Direct Read and Write of Device Registers
JTAG
Or
Debug
IF
Device
Logic
Blocks
Device
Register
File
Write.jtag ( ADDR:04h, DATA: 55h)
Read.jtag ( ADDR:0Ah, DATA read_var)
What you have to do
Debug using ATE Patterns at a
much lower, bit oriented level:
’01HL’
Strategy with Stored Response ATE
- Translate JTAG commands into
multiple parallel vectors
- Develop software wrapper to
dynamically generate patterns and
decode results
Strategy with Protocol Aware ATE
- Patternless commands to read and
write registers in native protocol
Potential benefits
- Faster program development
- Faster test time
- Up to 98% smaller pattern
sets
nWire
Protocol
EnginePayload
Protocol
Definition
18
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Cost of Test Reduction
Increasing site count for lowest COT
Instrument Pin Density Universal
Instrument
Test head EnablersMarket
Segment
Z-space DIB ModulesDevice
Family
DIB/Probe CardMother/Daughter Board
Device
Specific
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DIB Modules for multi-site DAC Testing
DC reference Module
20011 Test Technology Workshop November 16, 2011 James J. Ko
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FLEXConnect: Market Segment Enabler
FlexConnect Module
Teradyne Company Confidential
Improving Test Development time and increasing
high-site count DIB reliability
By reducing applications circuitry on the DIB
Existing Modules include
DC Enabler – (32) 1A Relays
High Current Switch Matrix – (4) 1:6 MUX’s
20011 Test Technology Workshop November 16, 2011 James J. Ko
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Towerless Probe for TSV and Bumped die
Prober
ProberProbe Card
Tester
PIBProbe tower
Standard Prober Docking Towerless Prober Docking
Tester
Probe Card
Standard Prober Docking
Instrument PIBProbe
Tower
Probe
Card
Probe
Head
pogos pogos Solder pads Probe Needlesinterposer
InstrumentProbe
Card
Probe
Head
Solder pads Probe Needles
Towerless Prober Docking
interposer
Probe Head
Probe Head
Advantages:
-Higher signal fidelity
-Lower tooling costs
-Better planarity with chuck
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Design Test Design LoopD
esig
n
Sim
ula
tio
n
On-Tester Debug/
Characterization
(hours/minutes)
•Timing/Levels
•Mixed Signal
•Repeatability
•Correlation
Pattern & Test
program. Gen.
events
transactions
ATPG
STDF
“off tester”
tools
“on tester”
tools
Failure Analysis / Yield Enhancement
EDA-based Pattern Viewer
• Simultaneous display of EDA and tester information
• Diagnose Physical Device Faults
2
3
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Summary: SOC ATE System Design for TFx
Complex SoC design and test demand
• Use more Sensors, H/W and S/W for better human interface
• Low power, high speed for mobility
• Re-use of 3rd party IP
• Use Asynchronous interfaces IP cores
• Low cost of test and high production efficiency
• Easy program development and ATE optimization tools for Time to Market
ATE system design for the new SoC and test demands
• High BW RF, high speed Digital, accurate DC
• Protocol Aware for testing Asynchronous independent IP cores
• Test IP reuse & collaborative development tools
• Multi-site test and Concurrent test for low COT
• Precise wafer probe interface
• Link to EDA tools -Test to Design for Time to Market
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