Slide title In CAPITALS 50 pt Slide subtitle 32 pt Baseband
Multicore challenge A view from the Baseband Research Team
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Multicore challenge2008-03-182 Baseband requirements & HW Hard
latency demands hard realtime Should be reconfigurable every
millisecond. Embedded All resources always very scarce Partly
Embarrassingly parallel, partly not. Scalability
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Multicore challenge2008-03-183 Baseband requirements & HW
Heterogeous (example: Cell) Special purpose accelerators Low power
> low clock frequency
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Multicore challenge2008-03-184 Challenges Deployment
Reconfiguration in runtime
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Multicore challenge2008-03-185 The dynamic challange Demodulator
Antennas Radio RX Receiver filter Extract user #0 FFT Extract user
#1 Extract user User data Decoder User data Decoder User data
Decoder AGC Scheduler Remove CP Demodulator Embarrassingly parallel
Latency limitAlgorithm split
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Multicore challenge2008-03-186 Challenges Deployment
Reconfiguration in runtime Programming model Engineering efficiency
Debugging Verification Heterogeous HW/SW? (Several types of
functions, HW, and languages in system (assembler, C, Erlang,
xtUML)) For how long can we continue to build on ASICs+classical
DSPs? How to be prepared for the new times to come?
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Multicore challenge2008-03-187
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Multicore challenge2008-03-188 Cambrian Explosion Proton
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Multicore challenge2008-03-189 Important multicore questions: How
to split a problem (e.g. de-interleaving) in unnaturally small
pieces in the most efficient way (mainly regarding latency)?
Different difficulties depending on target architecture Which of
the architectures on the market is the best for our purpose? How
could it be even better? Which of the architectures on the market
will be commercially successful? How is the relation between HW
& SW development in these typically HW centered companies?
Holistic? Cooperative? Ignorant?
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Multicore challenge2008-03-1810 Multicore hardware to keep an eye
on: ASIC hard as a rock FPGA soft as a chewing-gum. Single- and
few-core DSP & CPU Application Specific SOCs. Single- and
few-core DSP & CPU with off-load engine Hard off-load engines
Software-configurable off-load engines SIMD MIMD Multi-core DSP
& CPU TI DSP + Proton MPC8578
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Multicore challenge2008-03-1811 MPR view of the future: For a
project manager, the easy way out is to ignore the new extreme
architectures in favor of conventional solutions. In the old days,
nobody ever got fired for buying IBM. Today, the safe bets are
probably DSPs or ASSPs from major vendors like Analog Devices,
Broadcom, or TI. But taking the safe route may overlook a
more-flexible, higher-performance, lower- cost, lower-power
architecturealbeit one that requires more time to understand. A
competitor that spends that additional time might design a better
product. Such are the hazards of architectural abundance. (Tom R.
Halfhill)
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Multicore challenge2008-03-1812