Slide 1
6.071 Digital Logic 1
Flip-Flops
Q
Q
S R Q Q0011
0101
Q010
Q100
holdresetsetnot used
Cross-NOR SR flip-flop
Reset
Set
Q
Q
S R Q Q0011
0101
101Q
110Q
not usedresetsethold
Cross-NAND SR flip-flop
Reset
Set
Slide 2
6.071 Digital Logic 2
Clocked Level-Triggered NAND SR Flip-Flop
CLK S R Q Q00110011
01010101
QQQQ001Q
QQQQ010Q
holdhold SR inputshold disabledholdholdreset SR inputsset enabledindeterminate
R
S
Q
Q
CLK NANDenable gates
SR flip-flop
00001111
Slide 3
6.071 Digital Logic 3
Edge-Triggered SR Flip-Flops
We can make the level triggered flip-flop more flexible (in terms oftiming control) by turning it into an edge-triggered flip-flop. Anedge-triggered flip-flop only samples the inputs during either a positive or negative clock edge. This conversion can be done by taking the clock signal and running it through a level-triggered, pulsegenerator network and taking the corresponding output as the clocksignal.
delay gate
X
YZ
CLK
CLK
YX
Z
Positive edge-triggered delay gate
X
YZ
CLK CLK
CLK
YX
Z
CLK
Negative edge-triggered
Slide 4
6.071 Digital Logic 4
Level and Edge Triggered Flip-Flop Symbols
SCLK
R
Q
Q
Q
Q
SCLKR
SCLK
R
Q
Q
Q
Q
SCLK
R
SCLK
R
Q
Q
Q
Q
SCLK
R
inverted output(complement)
no triangle meanslevel-triggered
no bubblesmeans active-HIGH input
no bubble next totriangle means positiveedge-triggered input
triangle meansedge-triggered
edge-triggered
bubble next to triangle means negative edge-triggered input
Slide 5
6.071 Digital Logic 5
D-Type Flip-Flops
NAND madeinto an inverter
SR flip-flopR
SQ
QD
D (data)
Basic D-type flip-flop or latch D Q Q01
01
10
ResetSet
D
Q
Q
Q
logic symbol
Slide 6
6.071 Digital Logic 6
Divide by Two Circuit
CLK
D Q
Q
CLK↑
Note: Edge Detector
QQD
At clock pulse edge, Q goes toD
So every time there is a clock pulse, Q is set to the old value of D. Therefore, Q changes (as does D) but by the time D changes, the edge is past.
Slide 7
6.071 Digital Logic 7
Stop-Go Indicator
D
Q
QD
Q
300Ω
300Ω
redLED
Q
Q
D
green
red
greenLED
Slide 8
6.071 Digital Logic 8
Divide-by-Two Counter
D
Q
Q
QCLK
InIn/2
CLKD = Q
Q
Slide 9
6.071 Digital Logic 9
Synchronizer
D
Q
Q
QCLK
stopstart
A B ADQ
B
HoldHoldSet Set Reset
Slide 10
6.071 Digital Logic 10
Synchronizer 2
We see timing is important, so we want to synchronize signals.
DOn/Off Q
QCLK
out
clockedge
D onoff offQ
Q ⋅clock
Lined up with clock, but not result of pulse.
Slide 11
6.071 Digital Logic 11
JK Flip-Flops
pulsegeneratorClock (C)
J
K
Z
Q
Q
positiveedge-trigger
negativeedge-trigger
Q
Q
Q
J
C
K
Q
Q
Q
J
C
K
Negative edge-trigger
Positive edge-trigger
Slide 12
6.071 Digital Logic 12
JK Flip-Flops 2
0 R
S0
Rin is (0,X) ∴ output is high; Sin is(0,1) ∴ output is high.
∴ all outputs are high.
The problem is that you can not “hold” this condition. The input1,1 can only hold outputs of (0,1) or (1,0).
Slide 13
6.071 Digital Logic 13
JK Flip-Flops 3
C J K Q Q01↓↑↑↑↑
XXX0011
XXX0101
QQQQ01Q
QQQQ10Q
holdholdholdholdResetSetToggle
C J K Q Q01↑↓↓↓↓
XXX0011
XXX0101
QQQQ01Q
QQQQ10Q
holdholdholdholdResetSetToggle
Positive edge-trigger
Negative edge-trigger
Slide 14
6.071 Digital Logic 14
JK Flip-Flop with Preset and Clear
Q
PRE
K
CLK
Q
CLR
J
Slide 15
6.071 Digital Logic 15
JK Flip-Flop with Preset and Clear(Negative Edge-Triggered)
Q
Q
Q
J
C
K
PRE
CLR
PRE CLR CLK J K Q Q01011111
10011111
XXX↓↓↓↓
↑ 0,1
XXX00111
XXX01011
101
Q000
Q0Q0
011
Q000
Q0Q0
PresetClearnot usedholdResetSetTogglehold
Q0 = state of Q before HIGH-to-LOW edge of clock.
Slide 16
6.071 Digital Logic 16
JK Flip-Flop with Preset and Clear(Positive Edge-Triggered)
Q
Q
Q
J
C
K
PRE
CLR
PRE CLR CLK J K Q Q01011111
10011111
XXX↑↑↑↑
↓ 0,1
XXX00111
XXX01011
101
Q000
Q0Q0
011
Q000
Q0Q0
PresetClearnot usedholdResetSetTogglehold
Q0 = state of Q before LOW-to-HIGH edge of clock.
Slide 17
6.071 Digital Logic 17
MOD-16 Ripple Counter/divide-by-2,4,8,16 Counter
+5V
CLK
CLRdivide-by-2 divide-by-4 divide-by-8 divide-by-16
Q0 Q1 Q2 Q3
CLRQ
QJ
K
PRE
CLRQ
QJ
K
PRE
CLRQ
QJ
K
PRE
CLRQ
QJ
K
PRE
(LSB) (MSB)
Q0Q1
Q2
Q3
CLKCLR
00000
00011
00102
00113
01004
01015
01106
01117
10008
10019
101010
101111
110012
110113
111014
111115
00000
00011
Slide 18
6.071 Digital Logic 18
MOD-16 Ripple Counter 2
+5V
CLK
CLRQ0 Q1 Q2 Q3
CLRQ
QJ
K
PRE
CLRQ
QJ
K
PRE
CLRQ
QJ
K
PRE
CLRQ
QJ
K
PRE
This circuit will count to up to 15 and then will disable (all bits = 0).Note: If one uses the Q’s as the counting bits instead of the Q’s, the Counter will count down from 15 and disable when 0 is reached.
Slide 19
6.071 Digital Logic 19
Q0Q1
Q2
Q3
CLKCLR
+5V
CLK
CLR divide-by-2 divide-by-4 divide-by-8 divide-by-16
Q0 Q1 Q2 Q3
CLRQ
QJ
K
PRE
CLRQ
QJ
K
PRE
CLRQ
QJ
K
PRE
CLRQ
QJ
K
PRE
(LSB) (MSB)
00000
00011
00102
00113
01004
01015
01106
01117
10008
10019
101010
101111
110012
110113
111014
111115
00000
00011
MOD-16 Synchronous Counter
Slide 20
6.071 Digital Logic 20
4-Bit Counter IC
The 7493’s internal structure consists of four JK flip-flops connectedto provide separate MOD-2 and MOD-8 sections. Both of theseare clocked by separate clock inputs. The MOD-2 uses Cp0 as itsclock input while MOD-8 uses Cp1.
14
1
2 3 12 9 8 11
Cp0
Cp1Q1 Q2 Q3Q0
7493
MR1 2
MR1 MR2 Q0 Q1 Q2 Q3
HLHL
HHLL
L L L Lcountcountcount
Slide 21
6.071 Digital Logic 21
74193 Presettable 4-bit Binary Up/Down Counter
CPU
CPD
MR
PLD0 D1 D2
D3
Q0 Q1 Q2Q3
TCU
TCD
11 15 1 10 9
14 3 2 6 7
5
4
12
13
MR1 PL CpU CpD D0 D1 D2 D3 Q0 Q1 Q2 Q3 TCU TCD
HHLLLHHL
XXLLLLHH
XXXLHH↑H
LHLXXHH↑
XXLHHLXX
XXLHHLXX
XXLHHLXX
XXLHHLXX
LLLLHH
LLLLHH
LLLLHH
LLLLHH
HHHHLHHH
LHLHHHHH
Count upCount down
Reset
Parallel load
count upcount down
Inputs Outputs
H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH voltage transition
Slide 22
6.071 Digital Logic 22
Block Diagrams of Various Shift Registers
Serial in / Serial out:
1 0 1 1 0 1 0 0Serial in… 0 1 0
Serial out0 0 1…
Parallel in / Serial out:
1 0 1 1 0 1 0 0
Parallel in
Serial out0 0 1…
1 0 1 1 0 1 0 0
Serial in / Parallel out:
1 0 1 1 0 1 0 0Serial in… 0 1 0
1 0 1 1 0 1 0 0Parallel out
Slide 23
6.071 Digital Logic 23
Creating Deviceston toff ton
Some device creating power -There are two modes for destruction1.) Short term ton is too long. Instantaneous heat load
too high. Assume no heat dissipation during ton.2.) long term - duty cycle ton/toff too high.
∴ Test for 2 conditionston < tmaxton/toff < duty cycle
ON
ON
ON
clock/n
clock-tc ≡ period
up down resetzero?overflow
MSB LSBcounter
n-bits
If overflow trigger relaytc⋅ 2n = tmax
If zero disable, clock untilnext ↑ edge of ON
Slide 24
6.071 Digital Logic 24
Problem
Explain why mon-stable is not so useful.
Solve problem using:
1x 555 - clockflip/flops, simple logic …1x up/down counter
borrowcarryclear
Slide 25
6.071 Digital Logic 25
4-bit Serial in/Serial out Shift Registers
1 0 1 1Serial in… 0 1 0
Serial out0 0 1 …
1 1 0 1Serial out… 1 0 0
Serial in0 1 0 …
Shift Left
Shift Right
D0 Q0
CLKf-f 0
D1 Q1
CLKf-f 1
D2 Q2
CLKf-f 2
D3 Q3
CLKf-f 3
D3 Q3
CLKf-f 0
D2 Q2
CLKf-f 0
D1 Q1
CLKf-f 0
D0 Q0
CLKf-f 0
clock
SerialOutput
SerialInput
clock
SerialInput
SerialOutput
Slide 26
6.071 Digital Logic 26
Parallel-to-Serial Shift Register
D0 Q0CLKf-f 0
D1 Q1CLKf-f 1
D2 Q2CLKf-f 2
D3 Q3CLKf-f 3
D0 D1 D2 D3
CLKinhibitCLK
SHIFT/LOAD
SHIFT LOAD
Serial output
ClockClock inhibit
SHIFT/LOADD0
D1
D2
D3
Serial out 1 1 0 1Inhibit Serial Shift
Slide 27
6.071 Digital Logic 27
JK Parallel-to-Serial Shift Register
J
K
QCLK
J
K
QCLK
J
K
QCLK
J
K
QCLK
Load/Shift
clock
Serial output
D0
D1 D2 D3
Slide 28
6.071 Digital Logic 28
8-Bit Serial-to-Parallel Data Converter
VCCMRDSb
DSa
CLK
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
345610111213
256912151619
3478
13141718
CLKGND
Divide-by-8counter
OctalD-typeFlip-flop
8-bitParallel
word
1 201492
8
1
107
+5V
Serial datainput
clock
Slide 29
6.071 Digital Logic 29
8-Bit Parallel-to-Serial Interface
D0
D1D2D3D4D5D6D7
111213143456
00100110
Parallel in
ASCII
“&”
0100110
Parallel loadClock enable
clock
PL
CE
CLK
DS GND
115
2
Q7
Q7
VCC
+5V
7
900100110
LSB comesout first
Serial Device
16
810
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