5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347 Internet: http://www.latticesemi.com
GAL®22V10 Device Datasheet September 2010
All Devices Discontinued! Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status.
Product Line Ordering Part Number Product Status Reference PCN
GAL22V10D
GAL22V10D-7LP
Discontinued
PCN#09-10 GAL22V10D-7LPN
GAL22V10D-10LP
PCN#13-10
GAL22V10D-10LPN
GAL22V10D-15LP
GAL22V10D-15LPN
GAL22V10D-25LP
GAL22V10D-25LPN
GAL22V10D-7LPI PCN#09-10
GAL22V10D-7LPNI
GAL22V10D-10LPI
PCN#13-10
GAL22V10D-10LPNI
GAL22V10D-15LPI
GAL22V10D-15LPNI
GAL22V10D-20LPI
GAL22V10D-20LPNI
GAL22V10D-25LPI
GAL22V10D-25LPNI
GAL22V10D-10QP
GAL22V10D-10QPN
GAL22V10D-15QP
GAL22V10D-15QPN
GAL22V10D-25QP
GAL22V10D-25QPN
GAL22V10D-10LS
PCN#06-07 GAL22V10D-15LS
GAL22V10D-25LS
GAL22V10D-4LJ PCN#09-10
GAL22V10D-4LJN
GAL22V10D-5LJ PCN#13-10
GAL22V10D-5LJN
5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347 Internet: http://www.latticesemi.com
Product Line Ordering Part Number Product Status Reference PCN
GAL22V10D (Cont’d)
GAL22V10D-7LJ
Discontinued
PCN#13-10
GAL22V10D-7LJN
GAL22V10D-10LJ
GAL22V10D-10LJN
GAL22V10D-15LJ
GAL22V10D-15LJN
GAL22V10D-25LJ
GAL22V10D-25LJN
GAL22V10D-7LJI
PCN#09-10 GAL22V10D-7LJNI
GAL22V10D-10LJI
GAL22V10D-10LJNI
GAL22V10D-15LJI
PCN#13-10
GAL22V10D-15LJNI
GAL22V10D-20LJI
GAL22V10D-20LJNI
GAL22V10D-25LJI
GAL22V10D-25LJNI
GAL22V10D-10QJ
GAL22V10D-10QJN
GAL22V10D-15QJ
GAL22V10D-15QJN
GAL22V10D-25QJ
GAL22V10D-25QJN
Specifications GAL22V10
1
2 28
NC
I/CL
K
II
I
I
I
I
I
I
NC NC
NC
GN
D
II I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Vcc I/O
/Q
I/O/Q
I/O/Q
4 2625
1918
21
23
16141211
9
7
5
Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY— 4 ns Maximum Propagation Delay— Fmax = 250 MHz— 3.5 ns Maximum from Clock Input to Data Output— UltraMOS® Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and UVCMOS 22V10 Devices• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR
— 90mA Typical Icc on Low Power Device— 45mA Typical Icc on Quarter Power Device
• E2 CELL TECHNOLOGY— Reconfigurable Logic— Reprogrammable Cells— 100% Tested/100% Yields— High Speed Electrical Erasure (<100ms)— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS— 100% Functional Testability
• APPLICATIONS INCLUDE:— DMA Control— State Machine Control— High Speed Graphics Processing— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONSESCRIPTION
Description
The GAL22V10, at 4ns maximum propagation delay time, combinesa high performance CMOS process with Electrically Erasable (E2)floating gate technology to provide the highest performance avail-able of any 22V10 device on the market. CMOS circuitry allowsthe GAL22V10 to consume much less power when compared tobipolar 22V10 devices. E2 technology offers high speed (<100ms)erase times, providing the ability to reprogram or reconfigure thedevice quickly and efficiently.
The generic architecture provides maximum design flexibility byallowing the Output Logic Macrocell (OLMC) to be configured bythe user. The GAL22V10 is fully function/fuse map/parametric com-patible with standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,DC, and functional testing during manufacture. As a result, Lat-tice Semiconductor delivers 100% field programmability and func-tionality of all GAL products. In addition, 100 erase/write cycles anddata retention in excess of 20 years are specified.
GAL22V10High Performance E2CMOS PLD
Generic Array Logic™
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subjectto change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 2006Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
GAL22V10Top View
PLCC
1
12 13
24I/CLK
I
I
I
I
I
I
I
I
I
I
GND
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
6
18
GAL22V10
DIP
22v10_12
Functional Block Diagram
Pin Configuration
SOIC
GAL22V10Top View
Lead-Free
Package
Options
Available!
1 121324
I I I I I I I I IG
ND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
618
I/CL
K IV
cc
I/O/Q
PROGRAMMABLE
AND-ARRAY
(132X44)
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/CLK
I
I
I
I
I
I
I
I
I
I
RESET
PRESET
8
10
12
14
16
16
14
12
10
8
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
ALL DEVIC
ES
DISCONTINUED
Specifications GAL22V10
2
Conventional PackagingCommercial Grade Specifications
Industrial Grade Specifications
GAL22V10 Ordering Information
)sn(dpT )sn(usT )sn(ocT )Am(ccI #gniredrO egakcaP
5.7 5 5.4 061 01V22LAG D IPL7- PIDcitsalPniP-42
5.4 5.4 061 01V22LAG D IJL7- CCLPdaeL-82
01 7 7 061 01V22LAG D IPL01- PIDcitsalPniP-42
061 01V22LAG D IJL01- CCLPdaeL-82
51 01 8 031 G IPL51-D01V22LA PIDcitsalPniP-42
031 IJL51-D01V22LAG CCLPdaeL-82
02 41 01 031 IPL02-D01V22LAG PIDcitsalPniP-42
031 IJL02-D01V22LAG CCLPdaeL-82
52 51 51 031 IPL52-D01V22LAG PIDcitsalPniP-42
031 IJL52-D01V22LAG CCLPdaeL-82
)sn(dpT )sn(usT )sn(ocT )Am(ccI #gniredOr geakcaP
4 5.2 5.3 041 JL4-D01V22LAG CCLPdaeL-82
5 3 4 041 JL5-D01V22LAG CCLPdaeL-82
5.7 5.4 5.4 041 PL7-D01V22LAG PIDcitsalPniP-42
5.4 5.4 041 JL7-D01V22LAG CCLPdaeL-82
01 7 7 55 PQ01-D01V22LAG PIDcitsalPniP-42
55 JQ01-D01V22LAG CCLPdaeL-82
90
90
130
90
LP01-D01V22LAG PIDcitsalPniP-42
031 JL01-D01V22LAG CCLPdaeL-82
03 LS101-D01V22LAG CIOSniP-42
51 01 8 55 PQ51-D01V22LAG PIDcitsalPniP-42
55 JQ51-D01V22LAG CCLPdaeL-82
LP51-D01V22LAG PIDcitsalPniP-42
LJ51-D01V22LAG CCLPdaeL-82
LS151-D01V22LAG CIOSniP-42
52 51 51 55 PQ52-D01V22LAG PIDcitsalPniP-42
55 JQ52-D01V22LAG CCLPdaeL-82
09 PL52-D01V22LAG piDcitsalPniP-42
09 JL52-D01V22LAG CCLPdaeL-82
09 S1L52-D01V22LAG CIOSniP-42
1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.
ALL DEVIC
ES
DISCONTINUED
Specifications GAL22V10
3
Part Number Description
Lead-Free PackagingCommercial Grade Specifications
)sn(dpT )sn(usT )sn(ocT )Am(ccI #gniredrO egakcaP
4 5.2 5.3 041 NJL4-D01V22LAG CCLPdaeL-82eerF-daeL
5 3 4 041 NJL5-D01V22LAG CCLPdaeL-82eerF-daeL
5.7 5.4 5.4 041 NPL7-D01V22LAG PIDcitsalPniP-42eerF-daeL
5.4 5.4 041 NJL7-D01V22LAG CCLPdaeL-82eerF-daeL
01 7 7 55 NPQ01-D01V22LAG PIDcitsalPniP-42eerF-daeL
55 NJQ01-D01V22LAG CCLPdaeL-82eerF-daeL
031 NPL01-D01V22LAG PIDcitsalPniP-42eerF-daeL
031 NJL01-D01V22LAG CCLPdaeL-82eerF-daeL
51 01 8 55 NPQ51-D01V22LAG PIDcitsalPniP-42eerF-daeL
55 NJQ51-D01V22LAG CCLPdaeL-82eerF-daeL
09 NPL51-D01V22LAG PIDcitsalPniP-42eerF-daeL
09 NJL51-D01V22LAG CCLPdaeL-82eerF-daeL
52 51 51 55 NPQ52-D01V22LAG PIDcitsalPniP-42eerF-daeL
55 NJQ52-D01V22LAG CCLPdaeL-82eerF-daeL
09 NPL52-D01V22LAG piDcitsalPniP-42eerF-daeL
09 NJL52-D01V22LAG CCLPdaeL-82eerF-daeL
Industrial Grade Specifications
)sn(dpT )sn(usT )sn(ocT )Am(ccI #gniredrO egakcaP
5.7 5 5.4 061 INPL7-D01V22LAG PIDcitsalPniP-42eerF-daeL
5.4 5.4 061 INJL7-D01V22LAG CCLPdaeL-82eerF-daeL
01 7 7 061 INPL01-D01V22LAG PIDcitsalPniP-42eerF-daeL
061 INJL01-D01V22LAG CCLPdaeL-82eerF-daeL
51 01 8 031 INPL51-D01V22LAG PIDcitsalPniP-42eerF-daeL
031 INJL51-D01V22LAG CCLPdaeL-82eerF-daeL
02 41 01 031 INPL02-D01V22LAG PIDcitsalPniP-42eerF-daeL
031 INJL02-D01V22LAG CCLPdaeL-82eerF-daeL
52 51 51 031 INPL52-D01V22LAG piDcitsalPniP-42eerF-daeL
031 INJL52-D01V22LAG CCLPdaeL-82eerF-daeL
Blank = Commercial I = Industrial
Grade
PackagePowerL = Low PowerQ = Quarter Power
Speed (ns)
XXXXXXXX XX X XX X
Device Name
_
P = Plastic DIP PN = Lead-Free Plastic DIP J = PLCC JN = Lead-Free PLCC S = SOIC
GAL22V10D
ALL DEVIC
ES
DISCONTINUED
Specifications GAL22V10
4
GAL22V10 OUTPUT LOGIC MACROCELL (OLMC)
Each of the Macrocells of the GAL22V10 has two primary functionalmodes: registered, and combinatorial I/O. The modes and theoutput polarity are set by two bits (SO and S1), which are normallycontrolled by the logic compiler. Each of these two primary modes,and the bit settings required to enable them, are described belowand on the following page.
REGISTEREDIn registered mode the output pin associated with an individualOLMC is driven by the Q output of that OLMC’s D-type flip-flop.Logic polarity of the output signal at the pin may be selected byspecifying that the output buffer drive either true (active high) orinverted (active low). Output tri-state control is available as an in-dividual product-term for each OLMC, and can therefore be definedby a logic equation. The D flip-flop’s /Q output is fed back into theAND array, with both the true and complement of the feedbackavailable as inputs to the AND array.
NOTE: In registered mode, the feedback is from the /Q output ofthe register, and not from the pin; therefore, a pin defined as reg-istered is an output only, and cannot be used for dynamicI/O, as can the combinatorial pins.
COMBINATORIAL I/OIn combinatorial mode the pin associated with an individual OLMCis driven by the output of the sum term gate. Logic polarity of theoutput signal at the pin may be selected by specifying that the outputbuffer drive either true (active high) or inverted (active low). Out-put tri-state control is available as an individual product-term foreach output, and may be individually set by the compiler as either“on” (dedicated output), “off” (dedicated input), or “product-termdriven” (dynamic I/O). Feedback into the AND array is from the pinside of the output enable buffer. Both polarities (true and inverted)of the pin are fed back into the AND array.
The GAL22V10 has a variable number of product terms per OLMC.Of the ten available OLMCs, two OLMCs have access to eightproduct terms (pins 14 and 23, DIP pinout), two have ten productterms (pins 15 and 22), two have twelve product terms (pins 16 and21), two have fourteen product terms (pins 17 and 20), and twoOLMCs have sixteen product terms (pins 18 and 19). In additionto the product terms available for logic, each OLMC has an addi-tional product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmedto be true or inverting, in either combinatorial or registered mode.This allows each output to be individually configured as either activehigh or active low.
The GAL22V10 has a product term for Asynchronous Reset (AR)and a product term for Synchronous Preset (SP). These two prod-uct terms are common to all registered OLMCs. The AsynchronousReset sets all registers to zero any time this dedicated product termis asserted. The Synchronous Preset sets all registers to a logicone on the rising edge of the next clock pulse after this product termis asserted.
NOTE: The AR and SP product terms will force the Q output of theflip-flop into the same state regardless of the polarity of the output.Therefore, a reset operation, which sets the register output to a zero,may result in either a high or low at the output pin, depending onthe pin polarity chosen.
A R
S P
D
Q
QC L K
4 T O 1M U X
2 T O 1M U X
Output Logic Macrocell (OLMC)
Output Logic Macrocell ConfigurationsALL DEVIC
ES
DISCONTINUED
Specifications GAL22V10
5
ACTIVE HIGHACTIVE LOW
ACTIVE HIGHACTIVE LOW
S0 = 1S1 = 1
S0 = 0S1 = 1
S0 = 0S1 = 0
S0 = 1S1 = 0
A R
S P
D Q
QC L K
A R
S P
D Q
QC L K
Registered Mode
Combinatorial Mode
ALL DEVIC
ES
DISCONTINUED
Specifications GAL22V10
6
DIP (PLCC) Package Pinouts1 (2)
22 (26)OLMCS0�
5810�S1�
5811
0440�.�.�.�.�
0880
2 (3)
ASYNCHRONOUS RESET�(TO ALL REGISTERS)
0 4 8 12 16 20 24 28 32 36 40
SYNCHRONOUS PRESET�(TO ALL REGISTERS)
10 (12)
0000
5764
0044�.�.�.�
039623 (27)S0�
5808�S1�
5809
21 (25)OLMCS0�
5812�S1�
5813
0924�.�.�.�.�.�
1452
3 (4)
4 (5)
5 (6)
20 (24)OLMCS0�
5814�S1�
5815
1496�.�.�.�.�.�.�
2112
19 (23)OLMC
S0�5816�S1�
5817
2156�.�.�.�.�.�.�.�
2860
18 (21)OLMC
S0�5818�S1�
5819
2904�.�.�.�.�.�.�.�
3608
17 (20)OLMCS0�
5820�S1�
5821
3652�.�.�.�.�.�.�
4268
OLMCS0�
5822�S1�
5823
4312�.�.�.�.�.�
4840
8 (10)
16 (19)
15 (18)OLMCS0�
5824�S1�
5825
4884�.�.�.�.�
5324
9 (11)5368�
.�
.�
.�5720
14 (17)OLMCS0�
5826�S1�
5827
7 (9)
6 (7)
11 (13) 13 (16)
8
10
14
16
12
12
16
14
10
8 OLMC
Electronic Signature 5828, 5829 ... ... 5890, 5891
L�S�B
M�S�B
Byte 7 Byte 6 Byte 5 Byte 4 Byte 2 Byte 1 Byte 0Byte 3
GAL22V10 Logic Diagram / JEDEC Fuse Map
ALL DEVIC
ES
DISCONTINUED
Specifications GAL22V10
7
Supply voltage VCC
....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to VCC
+1.0VOff-state output voltage applied........... -2.5 to V
CC +1.0V
Storage Temperature.................................. -65 to 150°CAmbient Temperature with
Power Applied ......................................... -55 to 125°C1. Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. Theseare stress only ratings and functional operation of the deviceat these or at any other conditions above those indicated inthe operational sections of this specification is not implied(while programming, follow the programming specifications).
Commercial Devices:Ambient Temperature (T
A) ............................. 0 to +75°C
Supply voltage (VCC
) with Respect to Ground ..................... +4.75 to +5.25V
Industrial Devices:Ambient Temperature (T
A) ............................ -40 to 85°C
Supply voltage (VCC
) with Respect to Ground ..................... +4.50 to +5.50V
Specifications GAL22V10D
COMMERCIALICC Operating Power VIL = 0.5V VIH = 3.0V L-4/-5/-7 — 90 140 mA
Supply Current ftoggle = 15MHz Outputs Open L-10 — 90 130 mA
L-15/-25 — 75 90 mA
Q-10/-15/-25 — 45 55 mA
VIL Input Low Voltage Vss – 0.5 — 0.8 V
VIH Input High Voltage 2.0 — Vcc+1 V
IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 μA
IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 μA
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.4 V
VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
IOL Low Level Output Current — — 16 mA
IOH High Level Output Current — — –3.2 mA
IOS2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 — –130 mA
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL PARAMETER CONDITION MIN. TYP.3 MAX. UNITS
INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L-7/-10 — 90 160 mA
Supply Current ftoggle = 15MHz Outputs Open L-15/-20/-25 — 75 130 mA
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by testerground degradation. Characterized but not 100% tested.3) Typical values are at Vcc = 5V and TA = 25 °C
Absolute Maximum Ratings1 Recommended Operating Conditions
DC Electrical Characteristics
ALL DEVIC
ES
DISCONTINUED
Specifications GAL22V10
8
tpd A Input or I/O to Combinatorial Output 1 4 1 5 1 7.5 ns
tco A Clock to Output Delay 1 3.5 1 4 1 4.5 ns
tcf2 — Clock to Feedback Delay — 2.5 — 3 — 3 ns
tsu — Setup Time, Input or Fdbk before Clk↑ 2.5 — 3 — 4.5 — ns
th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — ns
A Maximum Clock Frequency with 167 — 142.8 — 111 — MHzExternal Feedback, 1/(tsu + tco)
fmax3 A Maximum Clock Frequency with 200 — 166 — 133 — MHzInternal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with 250 — 200 — 166 — MHzNo Feedback
twh — Clock Pulse Duration, High 2 — 2.5 — 3 — ns
twl — Clock Pulse Duration, Low 2 — 2.5 — 3 — ns
ten B Input or I/O to Output Enabled 1 5 1 6 1 7.5 ns
tdis C Input or I/O to Output Disabled 1 5 1 5.5 1 7.5 ns
tar A Input or I/O to Asynch. Reset of Reg. 1 4.5 1 5.5 1 9 ns
tarw — Asynch. Reset Pulse Duration 4.5 — 4.5 — 7 — ns
tarr — Asynch. Reset to Clk↑ Recovery Time 3 — 4 — 5 — ns
tspr — Synch. Preset to Clk↑ Recovery Time 3 — 4 — 5 — ns
Over Recommended Operating Conditions
UNITS
1) Refer to Switching Test Conditions section.2) Calculated from fmax with internal feedback. Refer to fmax Description section.3) Refer to fmax Description section. Characterized initially and after any design or process changes that may affect these
parameters.
PARAMTEST
COND.1 DESCRIPTION
SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS
CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V
CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
-5
MIN. MAX.
COM/INDCOM
-7
MIN. MAX.
AC Switching Characteristics
Capacitance (TA = 25°C, f = 1.0 MHz)
Specifications GAL22V10D
COM
-4
MIN. MAX.
ALL DEVIC
ES
DISCONTINUED
Specifications GAL22V10
9
tpd A Input or I/O to Comb. Output 1 10 3 15 3 20 3 25 ns
tco A Clock to Output Delay 1 7 2 8 2 10 2 15 ns
tcf2 — Clock to Feedback Delay — 2.5 — 2.5 — 8 — 13 ns
tsu — Setup Time, Input or Fdbk before Clk↑ 6 — 10 — 12 — 15 — ns
th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — ns
A Maximum Clock Frequency with 83.3 — 55.5 — 41.6 — 33.3 — MHzExternal Feedback, 1/(tsu + tco)
fmax3 A Maximum Clock Frequency with 110 — 80 — 45.4 — 35.7 — MHzInternal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with 125 — 83.3 — 50 — 38.5 — MHzNo Feedback
twh — Clock Pulse Duration, High 4 — 6 — 10 — 13 — ns
twl — Clock Pulse Duration, Low 4 — 6 — 10 — 13 — ns
ten B Input or I/O to Output Enabled 1 10 3 15 3 20 3 25 ns
tdis C Input or I/O to Output Disabled 1 9 3 15 3 20 3 25 ns
tar A Input or I/O to Asynch. Reset of Reg. 1 13 3 20 3 25 3 25 ns
tarw — Asynch. Reset Pulse Duration 8 — 15 — 20 — 25 — ns
tarr — Asynch. Reset to Clk↑ Recovery Time 8 — 10 — 20 — 25 — ns
tspr — Synch. Preset to Clk↑ Recovery Time 8 — 10 — 14 — 15 — ns
Specifications GAL22V10D
-10
MIN. MAX.
-25
MIN. MAX.
-20
MIN. MAX.
-15
MIN. MAX.
Over Recommended Operating Conditions
UNITS
1) Refer to Switching Test Conditions section.2) Calculated from fmax with internal feedback. Refer to fmax Description section.3) Refer to fmax Description section.
SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS
CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V
CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
PARAM.TEST
COND.1DESCRIPTION
COM / IND IND COM / INDCOM / IND
Capacitance (TA = 25°C, f = 1.0 MHz)
AC Switching Characteristics
ALL DEVIC
ES
DISCONTINUED
Specifications GAL22V10
10
Input or I/O to Output Enable/Disable
Registered Output
Combinatorial Output
VALID INPUTINPUT orI/O FEEDBACK
tpd
COMBINATORIALOUTPUT
INPUT orI/O FEEDBACK
REGISTEREDOUTPUT
CLK
VALID INPUT
tsu
tco
th
(external fdbk)1/ fmax
tentdis
INPUT orI/O FEEDBACK
OUTPUT
CLK
(w/o fdbk)
tw h tw l
1 / fm a x
Clock Width
REGISTEREDOUTPUT
CLK
INPUT orI/O FEEDBACK�DRIVING SP
tsu th
tco
tspr
R EGIST ER EDO U T P U T
CLK
tarw
tar
tarr
INPUT orI /O FEEDBACKDRIVING AR
fmax with Feedback
Asynchronous ResetSynchronous Preset
CLK
REGISTEREDFEEDBACK
tcf tsu
1/ fmax (internal fdbk)
Switching Waveforms
ALL DEVIC
ES
DISCONTINUED
Specifications GAL22V10
11
fmax with Internal Feedback 1/(tsu+tcf)
Note: fmax with external feedback is cal-culated from measured tsu and tco.
fmax with External Feedback 1/(tsu+tco)
Note: tcf is a calculated value, derived by sub-tracting tsu from the period of fmax w/internalfeedback (tcf = 1/fmax - tsu). The value of tcf isused primarily when calculating the delay fromclocking a register to a combinatorial output(through registered feedback), as shown above.For example, the timing from clock to a combi-natorial output is equal to tcf + tpd.
fmax with No Feedback
Note: fmax with no feedback may be lessthan 1/(twh + twl). This is to allow for aclock duty cycle of other than 50%.
REG I S TE RLOGICARR AY
tc ots u
C L K
REGISTERLOGICARRAY
CLK
tsu + th
CLK
REGISTER
LOGIC�ARRAY
tcf
tpd
fmax Descriptions
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Specifications GAL22V10
12
GAL22V10D-4 Output Load Conditions (see figure below)
Test Condition R1 CL
A 50Ω 50pF
B Z to Active High at 1.9V 50Ω 50pF
Z to Active Low at 1.0V 50Ω 50pF
C Active High to Z at 1.9V 50Ω 50pF
Active Low to Z at 1.0V 50Ω 50pF
Input Pulse Levels GND to 3.0V
Input Rise and D-4/-5/-7 1.5ns 10% – 90%
Fall Times D-10/-15/-20/-25 2.0ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure
3-state levels are measured 0.5V from steady-state activelevel.
TEST POINT
C *L
FROM OUTPUT (O/Q) �UNDER TEST
+5V
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R 2
R 1
Output Load Conditions (except D-4) (see figure below)
Test Condition R1 R2 CL
A 300Ω 390Ω 50pF
B Active High ∞ 390Ω 50pF
Active Low 300Ω 390Ω 50pF
C Active High ∞ 390Ω 5pF
Active Low 300Ω 390Ω 5pF
TEST POINT
Z0 = 50Ω, CL*FROM OUTPUT (O/Q)UNDER TEST
+1.45V
R1
Switching Test Conditions
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Specifications GAL22V10
13
Electronic Signature
An electronic signature (ES) is provided in every GAL22V10device. It contains 64 bits of reprogrammable memory that cancontain user-defined data. Some uses include user ID codes,revision numbers, or inventory control. The signature data isalways available to the user independent of the state of the se-curity cell.
The electronic signature is an additional feature not present inother manufacturers' 22V10 devices. To use the extra feature ofthe user-programmable electronic signature it is necessary tochoose a Lattice Semiconductor 22V10 device type when com-piling a set of logic equations. In addition, many device program-mers have two separate selections for the device, typically aGAL22V10 and a GAL22V10-UES (UES = User Electronic Sig-nature) or GAL22V10-ES. This allows users to maintain compat-ibility with existing 22V10 designs, while still having the option touse the GAL device's extra feature.
The JEDEC map for the GAL22V10 contains the 64 extra fusesfor the electronic signature, for a total of 5892 fuses. However,the GAL22V10 device can still be programmed with a standard22V10 JEDEC map (5828 fuses) with any qualified device pro-grammer.
Security Cell
A security cell is provided in every GAL22V10 device to preventunauthorized copying of the array patterns. Once programmed,this cell prevents further read access to the functional bits in thedevice. This cell can only be erased by re-programming thedevice, so the original configuration can never be examined oncethis cell is programmed. The Electronic Signature is always avail-able to the user, regardless of the state of this control cell.
Latch-Up Protection
GAL22V10 devices are designed with an on-board charge pumpto negatively bias the substrate. The negative bias is of sufficientmagnitude to prevent input undershoots from causing the circuitryto latch. Additionally, outputs are designed with n-channel pullupsinstead of the traditional p-channel pullups to eliminate any pos-sibility of SCR induced latching.
Device Programming
GAL devices are programmed using a Lattice Semiconductor-approved Logic Programmer, available from a number of manu-facturers (see the the GAL Development Tools section). Com-plete programming of the device takes only a few seconds. Eras-ing of the device is transparent to the user, and is done automati-cally as part of the programming cycle.
Typical Input Current
1 . 0 2 . 0 3 . 0 4 . 0 5 . 0- 6 0
0
- 2 0
- 4 0
0
In p u t Vo ltag e (V o lts)
Inp
ut
Cu
rre
nt
(uA
)
Output Register Preload
When testing state machine designs, all possible states and statetransitions must be verified in the design, not just those requiredin the normal machine operations. This is because certain eventsmay occur during system operation that throw the logic into anillegal state (power-up, line voltage glitches, brown-outs, etc.). Totest a design for proper treatment of these conditions, a way mustbe provided to break the feedback paths, and force any desired(i.e., illegal) state into the registers. Then the machine can besequenced and the outputs tested for correct next state condi-tions.
The GAL22V10 device includes circuitry that allows each regis-tered output to be synchronously set either high or low. Thus, anypresent state condition can be forced for test sequencing. Ifnecessary, approved GAL programmers capable of executing testvectors perform output register preload automatically.
Input Buffers
GAL22V10 devices are designed with TTL level compatible in-put buffers. These buffers have a characteristically high imped-ance, and present a much lighter load to the driving logic than bi-polar TTL devices.
The input and I/O pins also have built-in active pull-ups. As a re-sult, floating inputs will float to a TTL high (logic 1). However,Lattice Semiconductor recommends that all unused inputs andtri-stated I/O pins be connected to an adjacent active input, Vcc,or ground. Doing so will tend to improve noise immunity andreduce Icc for the device. (See equivalent input and I/O schemat-ics on the following page.)
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Specifications GAL22V10
14
(Vref Typical = 3.2V)
(Vref Typical = 3.2V)
Circuitry within the GAL22V10 provides a reset signal to all reg-isters during power-up. All internal registers will have their Q out-puts set low after a specified time (tpr, 1μs MAX). As a result, thestate on the registered output pins (if they are enabled) will beeither high or low on power-up, depending on the programmedpolarity of the output pins. This feature can greatly simplify statemachine design by providing a known state on power-up. Thetiming diagram for power-up is shown below. Because of the asyn-
chronous nature of system power-up, some conditions must bemet to guarantee a valid power-up reset of the GAL22V10. First,the Vcc rise must be monotonic. Second, the clock input mustbe at static TTL level as shown in the diagram during power up.The registers will reset within a maximum of tpr time. As in nor-mal system operation, avoid clocking the device until all input andfeedback path setup times have been met. The clock must alsomeet the minimum pulse width requirements.
Vcc
PIN
Vcc Vref
Active Pull-up Circuit
ESD ProtectionCircuit
ESD ProtectionCircuit
Vcc
PIN
Vcc (min.)
tpr
Internal RegisterReset to Logic "0"
Device PinReset to Logic "1"
twl
tsu
Device PinReset to Logic "0"
Vcc
C L K
INTERNAL REGISTER�Q - OUTPUT
ACTIVE LOW�OUTPUT REGISTER
ACTIVE HIGH�OUTPUT REGISTER
Vcc
PIN
VrefTri-StateControl
Active Pull-up Circuit
Feedback(To Input Buffer)
PIN
Feedback
Data Output
Typical Input Typical Output
Power-Up Reset
Input/Output Equivalent Schematics
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Specifications GAL22V10
15
Delta Tpd vs # of OutputsSwitching
-0.3
-0.2
-0.1
0
1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching
Del
ta T
pd (n
s)
RISEFALL
Delta Tco vs # of OutputsSwitching
-0.4
-0.3
-0.2
-0.1
0
1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching
Del
ta T
co (n
s)D
elta
Tco
(ns)
RISEFALL
Delta Tpd vs Output Loading
Output Loading (pF)
Del
ta T
pd (n
s)
RISEFALL
Delta Tco vs Output Loading
RISEFALL
Normalized Tpd vs Vcc
Nor
mal
ized
Tpd
Nor
mal
ized
Tpd
RISEFALL
Normalized Tco vs Vcc
RISEFALL
Normalized Tsu vs Vcc
Supply Voltage (V)Supply Voltage (V)Supply Voltage (V)
RISEFALL
Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp
1251007550250-25-551251007550250-25-55
300250200150100500
Output Loading (pF)
300250200150100500
Temperature (deg. C) Temperature (deg. C) Temperature (deg. C)
1251007550250-25-55
RISEFALL
RISEFALL
RISEFALL
5.55.2554.754.50.9
1.3
1.2
1.1
1
0.9
0.8
12
8
4
0
-4
12
8
4
0
-4
1.3
1.2
1.1
1
0.9
0.80.9
1
1.1
1.2
0.95
1
1.05
1.1
Nor
mal
ized
Tco
Nor
mal
ized
Tco
0.9
0.95
1
1.05
1.1
Nor
mal
ized
TN
orm
aliz
ed T
su
0.9
0.95
1
1.05
1.1
5.55.2554.754.5 5.55.2554.754.5
GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams
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Specifications GAL22V10
16
Vol vs Iol
0
0.2
0.4
0.6
0 5 10 15 20 25 30 35 40
Iol (mA)
Vol
(V)
Voh vs Ioh
0
1
2
3
4
0 5 10 15 20 25 30 35 40 45 50 55 60
Ioh(mA)V
oh (V
)
Voh vs Ioh
3.15
3.25
3.35
3.45
3.55
3.65
3.75
3.85
3.95
0.00 1.00 2.00 3.00 4.00 5.00
Ioh(mA)
Voh
(V)
Normalized Icc vs Vcc
0.8
0.9
1
1.1
1.2
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Nor
mal
ized
Icc
Normalized Icc vs Temp
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 88 100 125
Temperature (deg. C)
Nor
mal
ized
Icc
Normalized Icc vs Freq
0.95
1
1.05
1.1
1.15
1.2
1 15 25 50 75 100
Frequency (MHz)
Nor
mal
ized
Icc
Input Clamp (Vik)
Vik (V)
Iik (m
A)
Delta Icc vs Vin (1 input)6
5
4
3
2
1
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-3
100
80
60
40
20
0
-2.5 -2 -1.5 -1 -0.5 1
Vin (V)
Del
ta Ic
c (m
A)
GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams
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Specifications GAL22V10
17
GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic DiagramsNormalized Tpd vs Vcc
0.9
0.95
1
1.05
1.1
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Nor
mal
ized
Tpd
RISEFALL
Normalized Tco vs Vcc
0.95
1
1.05
1.1
4.5 4.75 5 5.25 5.5
Supply Voltage (V)N
orm
aliz
ed T
co
RISEFALL
Normalized Tsu vs Vcc
0.8
0.9
1
1.1
1.2
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Nor
mal
ized
Tsu
RISEFALL
Normalized Tpd vs Temp
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Nor
mal
ized
Tpd
RISEFALL
Normalized Tsu vs Temp
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Temperature (deg. C)N
orm
aliz
ed T
su
RISEFALL
Normalized Tco vs Temp
0.8
0.9
1
1.1
1.2
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Nor
mal
ized
Tco
RISEFALL
Delta Tpd vs # of Outputs Switching
-1.1
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching
Del
ta T
pd (
ns)
RISEFALL
Delta Tco vs # of Outputs Switching
-1.1
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching
Del
ta T
co (
ns)
RISEFALL
Delta Tpd vs Output Loading
-4
0
4
8
12
0 50 100 150 200 250 300
Output Loading (pF)
Del
ta T
pd (
ns)
RISEFALL
Delta Tco vs Output Loading
-4
0
4
8
12
0 50 100 150 200 250 300
Output Loading (pF)
Del
ta T
co (
ns)
RISEFALL
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Specifications GAL22V10
18
GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams
Vol vs Iol
0
0.1
0.2
0.3
0.4
0.5
0 5 10 15 20 25 30
Iol (mA)
Vol
(V
)
Voh vs Ioh
0
1
2
3
4
0 5 10 15 20 25 30 35 40
Ioh (mA)
Voh
(V
)
Voh vs Ioh
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
0.00 1.00 2.00 3.00 4.00 5.00
Ioh (mA)
Voh
(V
)
Normalized Icc vs Vcc
0.85
0.9
0.95
1
1.05
1.1
1.15
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Nor
mal
ized
Icc
Normalized Icc vs Temp
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 0 25 100
Temperature (deg. C)
Nor
mal
ized
Icc
Normalized Icc vs Freq
0.95
1
1.05
1.1
1.15
1.2
1 15 25 50 75 100
Frequency (MHz)
Nor
mal
ized
Icc
Input Clamp (Vik)0
10
20
30
40
50�
60
70
80
90
100-2.5 -2 -1.5 -1 -0.5 0
Vik (V)
Iik (
mA
)
Delta Isb vs Vin (1 input)
0
1
2
3
4
5
6
7
8
9
10
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Vin (V)
Del
ta Ic
c (m
A)
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Specifications GAL22V10
19
Normalized Tpd vs Vcc
0.9
0.95
1
1.05
1.1
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Nor
mal
ized
Tpd RISE
FALL
Normalized Tco vs Vcc
0.9
0.95
1
1.05
1.1
1.15
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Nor
mal
ized
Tco
RISEFALL
Normalized Tsu vs Vcc
0.8
0.9
1
1.1
1.2
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Nor
mal
ized
Tsu
RISEFALL
Normalized Tpd vs Temp
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Nor
mal
ized
Tpd
RISEFALL
Normalized Tsu vs Temp
0.75
0.85
0.95
1.05
1.15
1.25
1.35
1.45
-55 -25 0 25 50 75 100 125
Temperature (deg. C)N
orm
aliz
ed T
su
RISEFALL
Normalized Tco vs Temp
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Nor
mal
ized
Tco
RISEFALL
Delta Tpd vs # of OutputsSwitching
-1.2
-0.8
-0.4
0
1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching
Del
ta T
pd (n
s)
RISEFALL
Delta Tco vs # of OutputsSwitching
-1.2
-0.8
-0.4
0
1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching
Del
ta T
co (n
s)
RISEFALL
Delta Tpd vs Output Loading
-8
-4
0
4
8
12
16
20
0 50 100 150 200 250 300
Output Loading (pF)
Del
ta T
pd (n
s)
RISEFALL
Delta Tco vs Output Loading
-4
0
4
8
12
16
20
0 50 100 150 200 250 300
Output Loading (pF)
Del
ta T
co (n
s)
RISEFALL
GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams
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Specifications GAL22V10
20
Vol vs Iol
0
0.2
0.4
0.6
0 5 10 15 20 25 30 35 40
Iol (mA)
Vol
(V)
Voh vs Ioh
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0 20 40 60
Ioh (mA)V
oh (V
)
Voh vs Ioh
2.5
3
3.5
4
4.5
0.00 1.00 2.00 3.00 4.00 5.00
Ioh (mA)
Voh
(V)
Normalized Icc vs Vcc
0.8
0.9
1
1.1
1.2
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Nor
mal
ized
Icc
Normalized Icc vs Temp
0.75
0.85
0.95
1.05
1.15
1.25
1.35
-55 -25 0 25 50 88 100 125
Temperature (deg. C)
Nor
mal
ized
Icc
Normalized Icc vs Freq
0.9
1
1.1
1.2
1.3
1.4
1 15 25 50 75 100
Frequency (MHz)
Nor
mal
ized
Icc
Input Clamp (Vik)0
10�
20�
30�
40�
50�
60�
70�
80�
90-2.5 -2 -1.5 -1 -0.5 0
Vik (V)
Iik (m
A)
Delta Icc vs Vin (1 input)
0
1
2
3
4
5
6
7
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Vin (V)
Del
ta Ic
c (m
A)
GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams
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Specifications GAL22V10
21
Notes
Revision History
Date Version Change Summary
- 22v10_08 Previous Lattice release.
August 2004 22v10_09 Added lead-free package options.
July 2006 22v10_10 Corrected SOIC pin configuration diagram. Pin 13.
August 2006 22v10_11 Updated for lead-free package options.
December 2006 22v10_12 Corrected Icc in the Ordering Part Number section on pages 2-3.
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