ECE 4813 Dr. Alan Doolittle
ECE 4813
Semiconductor Device and Material Characterization
Dr. Alan Doolittle School of Electrical and Computer Engineering
Georgia Institute of Technology
As with all of these lecture slides, I am indebted to Dr. Dieter Schroder from Arizona State University for his generous contributions and freely given resources. Most of (>80%) the figures/slides in this lecture came from Dieter. Some of these figures are copyrighted and can be found within the class text, Semiconductor Device and Materials Characterization. Every serious microelectronics student should have a copy of this book!
ECE 4813 Dr. Alan Doolittle
Why do we need to know about Nano-electronic “materials” details? – A Case study of the evolution of the Transistor
Moore’s Law: The Growth of the Semiconductor Industry Moore’s law (Gordon Moore, co-founder of Intel, 1965): Empirical rule which predicts that the number of components per chip doubles every 18-24 months Moore’s Law turned out to be valid for more than 30 years (and still is!)
ECE 4813 Dr. Alan Doolittle
Why do we need to know about Nano-electronic “materials” details? – A Case study of the evolution of the Transistor
Moore’s Law: The Growth of the Semiconductor Industry
2000 Transistors
>1 Billion Transistors
ECE 4813 Dr. Alan Doolittle
Why do we need to know about Nano-electronic “materials” details? – A Case study of the evolution of the Transistor
from G. Moore, ISSCC 2003
Transistor functionality scales with transistor count not speed! Speed is less important.
ECE 4813 Dr. Alan Doolittle
Why do we need to know about Nano-electronic “materials” details? – A Case study of the evolution of the Transistor
How did we go from 4 Transistors/wafer to Billions/wafer? IBM 200 mm and 300 mm wafer http://www-3.ibm.com/chips/photolibrary
First Planar IC 1961, Fairchild http://smithsonianchips.si.edu/
1.5 mm
300 mm
ECE 4813 Dr. Alan Doolittle
Why do we need to know about Nano-electronic “materials” details? – A Case study of the evolution of the Transistor
Slide after Dr. John Cressler
ECE 4813 Dr. Alan Doolittle
The Basic Device in CMOS Technology is the MOSFET
Direction of Desired Current flow… …is controlled by an electric field… …but this field can also drive current through a small gate. Modern (pre-2009) transistors have more power loss in the gate circuit than the source -drain! New approaches are needed.
ECE 4813 Dr. Alan Doolittle
Why do we need to know about Nano-electronic “materials” details? – A Case study of the evolution of the Transistor
Early MOSFET: SiO2 Gate Oxide, Aluminum (Al) Source/Drain/Gate metals
Problem: As sizes shrank, devices became unreliable due to metallic spiking through the gate oxide.
Solution: Replace Metal Gate with a heavily doped poly-silicon.
This change carried us for decades with challenges in fabrication (lithography) being the primary barriers that were overcome …until…
ECE 4813 Dr. Alan Doolittle
Why do we need to know about Nano-electronic “materials” details? – A Case study of the evolution of the Transistor
Semi-Modern MOSFET (late 1990’s vintage): SiO2 Gate Oxide, Polysilicon gate metals, metal source/drain contacts and Aluminum metal interconnects
Problem: As interconnect sizes shrank, Aluminum lines became too resistive leading to slow RC time constants Solution: Replace Aluminum with multi-metal contacts (TiN, TaN, etc…) and copper interconnects.
This change carried us for ~ 1 decade with challenges in fabrication (lithography) being the primary barriers that were overcome …until…
ECE 4813 Dr. Alan Doolittle
Why do we need to know about Nano-electronic “materials” details? – A Case study of the evolution of the Transistor
from G. Moore, ISSCC 2003
Microprocessor Power Consumption
Gate
Gates became so thin that the leakage currents through the thin Gate insulator consumed more power than the drain-source circuit!
A new approach is needed!
ECE 4813 Dr. Alan Doolittle
from G. Moore, ISSCC 2003
GatetLeakageGate
Gate
Gateinsulatorinsulator
insulatorinsulator
eI
tVkD
EkD
∝
=
= Gate leakage current can be dramatically lowered by increasing Gate insulator thickness but to do so without changing the channel conductivity, you have to increase the dielectric constant of the insulator. NEW GATE INSULATORS FOR THE FIRST TIME IN 60 YEARS!!!!
Why do we need to know about Nano-electronic “materials” details? – A Case study of the evolution of the Transistor
ECE 4813 Dr. Alan Doolittle
2008 Vintage Intel Microprocessor
45 nm (~200 atoms)
Hafnium-Silicate (Oxide)
Strained Si (lower bandgap
– higher mobility)
ECE 4813 Dr. Alan Doolittle
2008 Vintage Intel Microprocessor 45 nm
(~200 atoms)
Hafnium-Silicate (Oxide)
Strained Si (lower bandgap
– higher mobility)
•High K Gate Dielectric:
•K of SiO2~3.9< Hafnium Silicate ~? < HfO2~ 22
•Deviation from SiO2 required reverting back to Metal Gates (no Poly-silicon)
•Limited Speed of Silicon partially overcome by using SiGe to “mechanically strain” Si channel resulting in Energy Band structure modification that increases electron/hole mobility.
ECE 4813 Dr. Alan Doolittle
Silicon in channel region is strained in two dimensions by placing a Si-Ge layer underneath (or more recently adjacent to) the device layer
Strained Si results in changes in the energy band structure of conduction and valence band, reducing lattice scattering
Benefit: increased carrier mobility, increased drive current (drain current)
from IEEE Spectrum, 10/2002
Strained Silicon MOSFET
Slide after Dr. Oliver Brandt
ECE 4813 Dr. Alan Doolittle
Change of basic transistor structure by introducing a double gate (or more general enclose the channel area by the gate)
Benefit: better channel control resulting in better device characteristics
Challenge: double-gate transistors require completely new device structures with new fabrication challenges
from IEEE Spectrum, 10/2002 Slide after Dr. Oliver Brandt
What is in the future? Double-Gate Transistors
ECE 4813 Dr. Alan Doolittle
Double-Gate Transistor Designs
Channel in chip plane
Channel perpendicular to chip plane with current flow in chip plane (FinFET)
Channel perpendicular to chip plane with current flow perpendicular to chip plane
from IEEE Spectrum, 10/2002
Slide after Dr. Oliver Brandt
ECE 4813 Dr. Alan Doolittle
FinFET Double-Gate Transistor
from http://www.intel.com/pressroom Slide after Dr. Oliver Brandt
ECE 4813 Dr. Alan Doolittle
Vertical multi-gate structures take us back to JFET like structures but now with the advantage of insulators. – Life is circular
ECE 4813 Dr. Alan Doolittle
SiO2 and SiO2/Si Interface Si, Si/SiO2 interface, SiO2 bulk, and oxide
defect structure
Si
D
B
Hydrogen
A
C
A: Si-Si Bond (Oxygen Vacancy) B: Dangling Bond C: Si-H Bond D: Si-OH Bond
Oxygen
Dangling Bond
ECE 4813 Dr. Alan Doolittle
Oxide Charges / Interface Traps
x x x x + + + ++ +
(1) (2)
(3)(4) SiO2
Si
Q=CV
Charge Type Location Cause Effect on Device
1) Dit(cm-2 eV-1), Nit (cm-2),
Qit ( C/cm2)
Interface Trapped Charge
SiO2/Si interface Dangling Bond, Hot electron damage,
contaminants
Junction Leakage Current, Noise,
Threshold Voltage Shift, Subthreshold
Slope
2) Nf, Qf (cm-2, C/cm2)
Fixed Charge Close to SiO2/Si interface
Si+ (?) Threshold Voltage Shift
3) Not, Qot (cm-2, C/cm2)
Oxide Trapped Charge
In SiO2
Trapped electrons and holes
Threshold Voltage Shift
4) Nm, Qm (cm-2, C/cm2)
Mobile Charge In SiO2 Na, K, Li Threshold Voltage Shift (time dependent)
ECE 4813 Dr. Alan Doolittle
1) Interface Trapped Charges
x x x x + + + ++ +
(1) (2)
(3)(4) SiO2
Si
Q=CV
Can be either positive or negative charge Due to:
Structural Defects Oxidation Induced Defects Metallic Impurities Radiation induced broken bonds Radiation induced broken bonds
Can be drastically improved by a low temperature (~450 C) anneal in a Hydrogen bearing gas.
ECE 4813 Dr. Alan Doolittle
2) Fixed Oxide Charges
x x x x + + + ++ +
(1) (2)
(3)(4) SiO2
Si
Q=CV
Generally positive charge and is related to oxidation conditions: Increases with decreasing oxidation temperature Can be reduced to a fixed (minimum value) by anneals in
inert gases Can be effected by rapid cooling
ECE 4813 Dr. Alan Doolittle
3) Oxide Trapped Charges
x x x x + + + ++ +
(1) (2)
(3)(4) SiO2
Si
Q=CV
Can be either positive or negative charge Due to electrons or holes trapped in the oxide:
Ionizing radiation (~>9 eV) Tunnel currents Breakdown
ECE 4813 Dr. Alan Doolittle
4) Mobile Charges
x x x x + + + ++ +
(1) (2)
(3)(4) SiO2
Si
Q=CV
Generally positive (sometimes negative but generally limited mobility if negative)
Due to contaminants (Na, K, Li) in the oxide: Gate voltage slowly drives the charge across the oxide
changing the threshold voltage and capacitance characteristics
Can lead to hysteresis in the CV curve Can lead to time dependent threshold voltages
ECE 4813 Dr. Alan Doolittle
MOS Capacitor MOS Capacitor (MOS-C) can be used to determine
Oxide charge Interface trapped charge Oxide thickness Flatband voltage Threshold voltage Substrate doping density Generation lifetime Recombination lifetime
ECE 4813 Dr. Alan Doolittle
MOS Capacitor MOS capacitor cross section and band diagram
0
E c /q
E F /q
t ox t ox +W
E i /q
E v /q φ
S
φ F
x
V G
V G
V ox
Surface Potential
Total Gate Voltage = VFB+Vox+φS
Voltage drop across oxide
ECE 4813 Dr. Alan Doolittle
MOS Capacitor Capacitance consists of
Cox: oxide capacitance Cp: accumulation capacitance Cb: bulk (space-charge region) capacitance Cn: inversion capacitance Cit: interface trap capacitance
Is generally given in units of Farads/cm2
Cox
Cp Cb Cn Citp
ECE 4813 Dr. Alan Doolittle
MOS Capacitor The capacitance is
G
G
dVdQC =
itnbp
s
its
ox
dQdQdQdQd
dQdQdVC
++++
+
−= φ1
itnbpox CCCCC
C
++++
= 111
sox
its
G
its
G
G
ddVdQdQ
dVdQdQ
dVdQC
φ++
−=+
−==
The charge is
)( itnbpitsG QQQQQQQ +++−=−−=
This gives
Assuming no oxide charge, gate charge = (-) semiconductor and interface charge
Because VFB is fixed
Hole, space charge, electron, and interface charge densities.
Math
ECE 4813 Dr. Alan Doolittle
MOS Capacitance Accumulation
Cp >> Cox→ CTotal~Cox
Depletion Cb ≈ <Cox ≈> Cit → CTotal<Cox
Inversion – low frequency Cn >> Cox → CTotal~Cox
Inversion – high frequency Cb ≈ Cox → CTotal<Cox
Cox
Accumulation
Cox
Cp Cb Cn Cit
Cox
Inversion - lf
Cox
Cp Cb Cn Cit
Cox
Cp Cb Cn Cit
Cb
Cox
Inversion - hf
Cox
Cp Cb Cn Cit
Cox
Cb Cit
Depletion
Accumulation: Negative VG draws holes
toward interface (Large
Qp=CpVG)
Depletion: Positive VG
pushes holes away from
interface (small Qp,n=Cp,nVG)
Inversion: large Positive VG
inverts surface region (Large
Qn=CnVG dominates over
Cb and Cit)
Qb=-qNAW (Cb>>Cit)
HF: When excitation is significantly
faster than the
generation lifetime
ECE 4813 Dr. Alan Doolittle
MOS Capacitance
0
0.2
0.4
0.6
0.8
1
-5 -3 -1 1 3 5
C/C
ox
Chf
Gate Voltage (V)
Clf
Cdd
CFB/Cox •
p-Substrate0
0.2
0.4
0.6
0.8
1
-5 -3 -1 1 3 5
C/C
ox
Chf
Gate Voltage (V)
Clf
Cdd
CFB/Cox•
n-Substrate
Sox
Sox
CCCCC+
=
Accumulation Cp >> Cox→ CTotal~Cox
Depletion Cb ≈ <Cox ≈> Cit → CTotal<Cox
Inversion – low frequency Cn >> Cox → CTotal~Cox
Inversion – high frequency Cb ≈ Cox → CTotal<Cox
Accumulation Depletion
LF Inversion, HF Inversion (VAC test faster than 1/τGeneration) or Deep Depletion (Vbias swept faster than τGeneration) Accumulation Depletion
LF Inversion, HF Inversion (VAC test faster
than 1/τGeneration) or Deep Depletion (Vbias swept
faster than τGeneration)
No inversion charge in deep depletion
CTotal~Cox in LF Inversion and Accumulation
ECE 4813 Dr. Alan Doolittle
MOS Capacitance – Generally Complex Mathematics
( ) ( )[ ]( )FS
UUUU
Di
sSlfS UUF
eeeeL
KUCSFSF
,11
2ˆ 0
,−+−
=−−ε
( ) ( ) ( )11, −−+−+= −−S
UUS
UUFS UeeUeeUUF SFSF
i
sDiS
S
SS nq
kTKLqkT
UUUU 2
0s
2;
/;ˆ εφ
===
( ) ( ) ( )[ ]( )FS
UUUU
Di
sShfS UUF
eeeeL
KUCSFSF
,111
2ˆ 0
,δε +−+−
=−−
( ) ( )( )( )
( )[ ]∫−−−
−−=
−S F
S
U
FS
UUUFSS
U
dUUUF
UeeeUUFUe
03,2
11,1δ
( )[ ] 121 0, −−+
=VVV
CCFBG
oxddS
ECE 4813 Dr. Alan Doolittle
MOS Capacitance
0
0.2
0.4
0.6
0.8
1
-5 -3 -1 1 3 5
C/C
ox
Chf
Gate Voltage (V)
Clf
Cdd
CFB/Cox •
p-Substrate0
0.2
0.4
0.6
0.8
1
-5 -3 -1 1 3 5
C/C
ox
Chf
Gate Voltage (V)
Clf
Cdd
CFB/Cox•
n-Substrate
Sox
Sox
CCCCC+
=
Diox
FSoxsSSFBoxSFBG LqK
UUFtkTKUVVVV ),(ˆ++=++= φφ
ECE 4813 Dr. Alan Doolittle
Low-Frequency Capacitance To measure the low-frequency C-VG curve, the inversion carriers must be able
to respond to both the ac gate voltage and the dc gate voltage sweep rate + ½ Cycle of VG: Driven displacement current (gate) must be less than the
available space charge (generation) current - ½ Cycle of VG: Recombination is fast enough to not be an issue
g
iscr
WqnJτ
= sVWtCWqn
dtdV
dtdVCJ
g
ox
oxg
iGGoxdispl =≤⇒=
ττ046.0
dtdV
vf G
geff
1=
in µm in nm
in µs
V G
W
V G
W 1
V G + ∆ V G
J scr
V G
W 2
V G - ∆ V G
W 1 > W > W 2
+++++ ++++++ ++ ++
Recombination Generation
ECE 4813 Dr. Alan Doolittle
Low-Frequency Capacitance The effective frequency is < 1 Hz
Very difficult to measure the capacitance Measure current
CIordt
dVCdt
dVdVdQ
dtdQI GG
G
~ ===
0
0.2
0.4
0.6
0.8
1
-4 -2 0 2 4
C/C
ox
Gate Voltage (V)
With Dit
0
0.2
0.4
0.6
0.8
1
-4 -2 0 2 4
C/C
ox
Gate Voltage (V)
With Dit
ECE 4813 Dr. Alan Doolittle
Flatband Voltage (and Capacitance)
+ + +
+
Most Junior level classes assume: A metal can be selected that aligns perfectly with the fermi-level in the
semiconductor No charges exist in the Oxide
These are generally not true (once again, we lied to you), leading to a “pre-bias” on the device
This shifts the CV Curve and requires a voltage be applied to obtain “flat band” conditions.
To determine VFB, one must compare the measured to theoretical CV curves and thus must know the theoretical flatband capacitance
ECE 4813 Dr. Alan Doolittle
Flatband Capacitance The flatband voltage is that gate voltage at which the
capacitance is the flatband capacitance
( ) A
SSD
D
SFBS
FBSox
FBSoxFB Nq
kTKnpq
kTKLL
KCCC
CCC 2
02
00,
,
, ;; εεε≈
+==
+=
0
0.2
0.4
0.6
0.8
1
1014 1015 1016 1017 1018 1019
1000 nm500 nm200 nm100 nm50 nm20 nm10 nm7 nm5 nm3 nmtox = 2nm
CFB
/Cox
NA (cm-3)
ECE 4813 Dr. Alan Doolittle
Flatband Voltage Flatband voltage depends on various gate, semiconductor,
and oxide parameters
( ) ( ) ( ) ( ) ( )
−
−
−
−= ∫∫
ox
Sitt
edOxideTrappoxox
t
Mobileoxoxox
fMSFB C
QdxxtxC
dxxtxCC
QV
oxox φρρφ00
11
++++
0 tox x
γ=0++++
0 tox x
γ=1
Weighted sum (integral) accounts for how far away the charge is from the oxide-semiconductor interface.
No effect on VFB Strong effect on VFB
ECE 4813 Dr. Alan Doolittle
Work Function Difference The work function difference, φMS, depends on the
Fermi level of the gate (polysilicon) and the substrate Assuming the gate is degenerately doped (i.e. fermi
level is in the majority carrier band…
( ) ( )substrategate FFSMMS φφφφφ −=−=
φF
Eg/2q
VFB
φFEg/2q
VFB
ECEi
EV
EF
n+ GateEF = EC
p+ GateEF = EV
ECE 4813 Dr. Alan Doolittle
Qf, φMS Measurements
Assume Qm = Qot = Qit = 0
Measure and plot VFB versus tox
oxox
fMS
ox
fMSFB t
KqN
CQV
0εφφ −=−=
0
0.2
0.4
0.6
0.8
1
-3 -2 -1 0 1 2
C/C
ox
Gate Voltage (V)
VFB
CFB/Cox
Ideal
ECE 4813 Dr. Alan Doolittle
Mobile Charge Bias-temperature stress (BTS)
Apply positive gate voltage to produce εox ≈ 106 V/cm at T = 150-200 °C for t = 5-10 min. Cool device with applied voltage; measure C-VG at room temperature
Repeat with negative gate voltage The gate voltage shift, ∆VFB, between the two curves is
due to mobile charge
oxFBm CVQ ∆−=
0
0.2
0.4
0.6
0.8
1
-4 -2 0 2 4
C/C
ox
Gate Voltage (V)
ECE 4813 Dr. Alan Doolittle
Mobile Charge Triangular voltage sweep
MOS-C is held at T = 200-300°C High-frequency C - VG and low-frequency I - VG measured
dtdQI G=
)(dt
dVCI FBlf −= α
( )[ ] ( )[ ]{ }12
1
1
GFBGFBG
V
V lf
VtVVtVdVCIG
G
−−−=
−∫
−
αα
( )[ ] ( )[ ]{ }ox
mGFBGFB C
QVtVVtV αα =−−− 12
mGox
V
V lf
QdVCCIG
G
αα −=
−∫
−
1
1
ECE 4813 Dr. Alan Doolittle
Mobile Charge Triangular Voltage Sweep (TVS) Measure hf and lf C-VG curves simultaneously at T ≈ 200°C Qm = area between lf and hf curves Suitable for gate oxides and interlevel dielectrics
∫−−= 2
1)(G
G
V
V Ghflfm dVCCQ
300
500
700
900
-3 -2 -1 0 1 2 3
Cap
acita
nce
(pF)
Gate Voltage (V)
Nm=1.3x1010 cm-2
tox=100 nm
4.1x109 cm-2
hf
lf
0200400600800
100012001400
-4 -3 -2 -1 0 1 2 3 4C
apac
itanc
e (p
F)
Gate Voltage (V)
T=120C
100 C80 C
60 C
10 C, 40 C
ECE 4813 Dr. Alan Doolittle
Interface Trapped Charge Quasi-static method High-frequency and low-frequency
C-VG curves are measured
itSox
lf
CCC
C
++
= 111
−
−== S
lfox
lfoxitit C
CCCC
qqCD 22
1
∆+
−= ∫ G
V
V ox
lfs dV
CCG
G
2
1
1φ
hfox
hfoxS CC
CCC−
=
0
0.2
0.4
0.6
0.8
1
-5 -3 -1 1 3 5
C/C
ox
Chf
Gate Voltage (V)
Clf (ideal)C'lf (with Dit)
•
−
−−
=oxhf
oxhf
oxlf
oxlfoxit CC
CCCC
CCqCD
/1/
/1/
2
ECE 4813 Dr. Alan Doolittle
Quasistatic Method Current flow through oxide causes
Interface state generation Oxide charge trappping
1010
1011
1012
1013
-0.2 0 0.2 0.4 0.6 0.8 1D
it (c
m-2
eV-1
)
Before stress
Surface Potential (V)
After stress
Data courtesy of W. Weishaar, Arizona State University
Gate Voltage (V)
Before Stress
After StressC/C
ox
1
0-2 0 2
.
ECE 4813 Dr. Alan Doolittle
Interface Trapped Charge Charge Pumping
Uses MOSFET Apply periodically varying gate voltage Measure resulting current at the substrate or
source/drain
p
n n
VR
VG
VR
Icp
t
p
n n
VR
VG
VR
Icp
t
(a) (b)
ECE 4813 Dr. Alan Doolittle
Charge Pumping
Cthn
Ce Nv
kTEEσ
τ ))(exp( 1−=
=−
fNvkTEE Cthn
C 2ln1
σ
sthpc pvσ
τ 1=
=−
fNv
kTEE VthpV 2
ln2
σ
+
−≈∆
fNv
fNvkTEE VthpCthn
g 2ln
2ln
σσ
EC
EV
∆E
To S/DChannel
Trappedelectrons
Hole Barrier
( )[ ]TGoxitGcp VVCEqDfAI −+∆= α
ECE 4813 Dr. Alan Doolittle
Charge Pumping Bilevel
Keep baseline constant, vary pulse height Vary baseline, keep pulse height constant
∆V
∆V
a
b
b
a
c
d
e∆V
Icp Icp
Vbase VFB VT
a
b
c
d
e
ba
WeakAccumulation
WeakInversion
ECE 4813 Dr. Alan Doolittle
MOSFET Subthreshold ID - VG Below VT, ID depends exponentially on VG
Slope change due to stress is very small for thin oxides
oxitA
oxoox
itA
ox
its
nkTVVqoD
tDWNx
tK
qDWNqC
DqCn
eII TG
)(1065.41
)(1
1
7
2
/)(
++=
++=
++=
=
−
−
ε
−=∆
BeforeSlopeAfterSlopekTCD ox
it 1
1
3.2
10-13
10-12
10-11
10-1010-9
10-8
10-7
10-6
0 0.2 0.4 0.6 0.8 1D
rain
Cur
rent
(A)
Gate Voltage (V)
∆Dit=5x1011cm-2eV-1
BeforeStress
After∆VT
ECE 4813 Dr. Alan Doolittle
Review Questions Name the four main charges in the oxide How is the low-frequency capacitance
measured? What is the flatband voltage and flatband
capacitance? Describe charge pumping. How does the subthreshold slope yield the
interface trap density?
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