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EEE 272 High Speed Digital Design
Lab 4: Ringing on a Transmission Line
Submitted by:
Prem Bhaskara
Under the Guidance of:
Dr. Milica Markovic
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Bounce Diagrams:
Draw the bounce diagram for a 100Ω transmission line terminated in a 200Ω resistance. The source is
a 10V step function, with internal resistance of 50Ω. The line is 10cm long. Dielectric inside the
transmission line is air. Draw 4 bounces. Label the time when the generator is turned on as 0. Label
each other time step at both load and generator sides.
Calculations of electrical length:
=ℎ
ℎ, =0.01
3 ∗ 1 08sec = 0.33
= 0.33
ℎ ℎ = 360
∗
=1
=
1
1= 1
= ∗ 360
=
(0.33 ∗ 360)
1= 120°
∴ = 120°
Calculation of reflection coefficient at the load and generator side:
= + +
= 10 + 10050 + 100
= 6.666
=200 − 100
200 + 100= 0.333
=50 − 100
50 + 100= −0.333
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Bounce Diagram:
Schematic:
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Fig. 1.4: Simulation Results
Thus our simulation results obtained match with our hand calculations.
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3. Ringing on a transmission lineMake a new schematic diagram in ADS and add Transient analysis simulator. Select the start, stop and
step time after you make the circuit.
1. Re-create diagrams in Figure 8-16, page 302, as discussed below.
(a) Place a Sources-Time Domain source VtPulse with rise-time of 0.5ns and frequency of 100MHz.
Add a 10 resistor in series with the generator. This resistance simulates the internal resistance of the
generator.
(b) Place an ideal transmission line on the schematic (TLIN), and connect it to the source.
(c) Set the transmission line impedance of the line to be 50-, and the length of the transmission line to
be 20% (then 30%, adn 40%) of the rise time of the VtPulse. Remember that you don't have to set the
electrical length of the line at 100MHz frequency. It's better if you set it at f=1GHz. Show calculations.
What is the actual length of this transmission line?
Ans:
To set the length of the transmission line to 20% of the rise time,
Electrical length = 2 * 180 * TD
Case 1: TD = 20 % or rise time
here, rise time = 0.5 ns, so TD = 0.5 ns * 20 / 100 = 0.1 ns
So, the electrical length (θ) = 2 * 180 * 0.1 = 36 degree
Circuit with 20% rise-time
Fig 1 Schematic
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Fig 1.1 Simulation
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Case 2: TD = 30 % or rise time
here, rise time = 0.5 ns, so TD = 0.5 ns * 30 / 100 = 0.15 ns
So, the electrical length (θ) = 2 * 180 * 0.15 = 54 degree
Circuit with 30% rise-time
Fig1.2 Schematic
Fig 1.3 Simulation
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Case 3: TD = 40 % or rise time
here, rise time = 0.5 ns, so TD = 0.5 ns * 40 / 100 = 0.2 ns
So, the electrical length (θ) = 2 * 180 * 0.2 = 72 degree
Circuit with 40% rise-time
Fig 1.4 Schematic
Fig 1.4 Schematic
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To calculate actual length (L),
TimeDelay (TD) = L / λ
Where, λ = C / ( freq *√ )Where, C = speed of light in air = 12 inches / ns
freq = 1 GHz
εr = 1
So, L = TD * λ = TD * C / freq
For case 1: TD = 0.1 ns
So, L = 0.1 * (12 /10-9) / 1 * 109 = 0.1 * 12 = 1.2 inches
For case 2: TD = 0.15 ns
So, L = 0.15 * (12 /10-9) / 1 * 109 = 0.15 * 12 = 1.8 inches
For case 3: TD = 0.2 ns
So, L = 0.2 * (12 /10-9) / 1 * 109 = 0.2 * 12 = 2.4 inches
(d) Leave the other side of the transmission line open.
(e) Label the generator side between the resistor and the line as vin and the resistor side as vout.
(f) Simulate the above circuit and show the input and output voltage as a function of time on the same
graph. What can you conclude? What is the maximum lenght of the line before signal-integrity
problems arise?
According to the simulation result, as we increase the time delay from 20% rise time to 40 % rise time,
the ringing also increases. We can conclude that if the time delay is short compared with the rise time,
the multiple bounces will be smeared over the rise time and it will be negligible ringing. If we decreasethe time delay less than 20%, we can hardly see any ringing.
The maximum length for an unterminated line before signal integrity problem arise is roughly:
Lenmax < RT
Where, Lenmax = the maximum length for an unterminated line, in inches
RT = the rise time , in nsec
Here, RT = 0.5 ns, so Length should be less than 0.5 inches.
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2. Repeat the above simulation if source-series termination is applied to rectify the problem. What is
the source-series termination? Explain what do you have to add to the circuit? How does that prevent
ringing?
Ans: Source-series termination : As we know, the origin of the ringing is the impedance discontinuities
at the source and the far end and the multiple reflections back and forth. To prevent this ringing, we can
add impedance on the source side, to match the impedance of the transmission line so that when the
reflected signal comes back to the source and if it sees the same impedance then it will not reflect back.
This addition of additional resistance, we call it as a source series termination as we add the additional
resistor in the series at the input of the transmission line, so we call it as source-series transmission.
In our circuit, the impedance of the transmission line is 50Ω and the impedance of the voltage source is
10Ω. To match the impedance at the input side with the impedance of the transmission line, we have to
add additional resistor of 40Ω in series with the source so that the total impedance will be 10Ω + 40Ω =
50Ω. We can see the addition of source-series termination resistor in the circuit shown below.
As we know, ringing happens only when there is a change in impedance in the transmission line. So,
when the reflected signal from far end travels back to the source and reaches the series terminating
resistance, it sees looking into the source resistance and that is just the same as transmission line; so thesignal will encounter no impedance change and there will be no reflection. Thus, source-series
termination prevents ringing. We can see the output result in the output waveform in below figure.
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Circuit with source-series termination resistor
Fig 2 Schematic
Fig2.1 Output of the simulation
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3. Re-create diagrams in Figure 8-20, page 308, for three widths of transmission line 25, 50! and 75 on
an electrically long line. What should the percent change of the characteristic impedance be to keep
the reflection noise below 5%? Demonstrate this with your simulations. What should the length of the
line be in terms of percent of rise time to keep the discontinuity negligible? Prove it with your
simulations.
Ans:
To keep the reflection noise to less than 5% of the voltage swing requires keeping the characteristic-
impedance change to less than 10%. The reason behind this is the impedance discontinuities contribute
to reflection noise. The more the impedance discontinuities, the more reflection noise.
We can see in our examples of three transmission lines with different characteristic impedance – 25, 50
and 75 Ω.
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Circuit with the transmission line : 25 Ω impedance
Fig 3 Schematic
Fig 3.1 Simulation
Circuit with the transmission line : 50 Ω impedance
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Fig 3.2 Schematic
Fig 3.3 Simulation Results
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Circuit with the transmission line: 75 Ω impedance
Fig3.4 Schematic
Fig3.5 Simulation
We can conclude from the simulation results that reflection noise can be kept low to 5% of the voltage
swing by keeping the characteristic impedance change to less than 10%. In simulation, we can see, when
we keep characteristic impedance change from 25 Ω to 50 Ω or 75 Ω to 50 Ω, there is always the
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reflection noise. But, when we kept the characteristic impedance change from 50 Ω to 50 Ω, there is no
reflection noise on the transmission line.
What should the length of the line be in terms of percent of rise time to keep the discontinuity
negligible? Prove it with your simulations.
To keep the discontinuity negligible, the length of the line should be such that the time delay (TD) is
shorter than 20% of the rise time.
To prove this, we have kept the length of the transmission line such that the timedelay will be 40%, 30%
and 20% of the risetime, the impedance as 25 ohm, and then we have observed the output for each
circuit.
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Circuit with the transmission line: length as 40% of the rise-time
Fig 3.6 Schematic
Fig 3.7 Simulation
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Circuit with the transmission line: length as 30% of the rise-time
Fig3.8 Schematic
Fig 3.9 Simulation
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Circuit with the transmission line: length as 20% of the rise-time
Fig 3.10 Schematic
Fig3.11 Simulation
Circuit with the transmission line: length as 10% of the rise-time
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Fig3.12 Schematic
Fig3.13 SimulationFrom the simulation results, we can conclude that the length of the line should be such that the time
delay will be less than 20% of the rise time to keep the discontinuity negligible.
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4. Re-create diagrams in Figure 8-22, page 311, for three stub lengths (0, 20%, 40% and 60% of RT.
What should be the stub’s time delay of the stub transmission line 25Ω, 50Ω and 75Ω on an
electrically long line? What is the maximum length of the stub in terms of percent of rise time that will
keep the reflection noise acceptable? Demonstrate this in your simulation, and find the actual length
of the stub in that case.
Short stub reflections
Figure 3.4.1: Schematics for Short stub reflections due to varying stub lengths (0%, 20%, 40%, and 60%
of RT)
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Figure 3.4.2: Simulations for Short stub reflections due to varying electrical lengths
We changed the electrical length of the transmission line stub to 0, 20%, 40% and 60% of rise time and
observed reflections for different electrical lengths.
Here we are given different stub lengths we have calculated electrical length for those different cases as
below:
Case 1: TD = 0 % of rise time
Here, rise time = 0.5 ns, so TD = 0.5 ns * 0 / 100 = 0
So, the electrical length (θ) = 2 * 180 * 0= 0 degree
Case 2: TD = 20 % of rise time
Here, rise time = 0.5 ns, so TD = 0.5 ns * 20 / 100 = 0.1 ns
So, the electrical length (θ) = 2 * 180 * 0.1 = 36 degree
Case 3: TD = 40 % of rise time
Here, rise time = 0.5 ns, so TD = 0.5 ns * 40 / 100 = 0.2 ns
So, the electrical length (θ) = 2 * 180 * 0.2 = 72 degree
Case 3: TD = 60 % of rise time
Here, rise time = 0.5 ns, so TD = 0.5 ns * 60 / 100 = 0.3 ns
So, the electrical length (θ) = 2 * 180 * 0.3 = 108 degree
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From our class notes we know that,
Maximum physical length = Speed of the signal * Time Delay
We know that for FR4 speed of the signal = 6 inches/nsec.
So the Maximum physical length can be given as
Case 1: TD = 0 % of rise time
Here, rise time = 0.5 ns, so TD = 0.5 ns * 0 / 100 = 0
So, the Maximum electrical length = 6inches/nsec * 0 = 0
Case 2: TD = 20 % of rise time
Here, rise time = 0.5 ns, so TD = 0.5 ns * 20 / 100 = 0.1 ns
So, the Maximum electrical length = 6inches/nsec * 0.1 = 0.6 inches
Case 3: TD = 40 % of rise time
Here, rise time = 0.5 ns, so TD = 0.5 ns * 40 / 100 = 0.2 ns
So, the Maximum electrical length = 6inches/nsec * 0.2 = 1.2 inches
Case 3: TD = 60 % of rise time
Here, rise time = 0.5 ns, so TD = 0.5 ns * 60 / 100 = 0.3 ns
So, the Maximum electrical length = 6inches/nsec * 0.3 = 1.8 inches
For: TD = 20 % of rise time it is close to TLIN with no discontinuity () whereas for = 60 % ofrise time, reflections are high because for higher length. Thus Shorter the length of the stub, lesser the
reflections due to discontinuity
Hence length should be shorter than the rise time of the signal as said in eqn 8.16 from the book
Maximum acceptable length for a discontinuity is _
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What is the maximum length of the stub in terms of percent of rise time that will keep the reflection
noise acceptable? Demonstrate this in your simulation, and find the actual length of the stub in that
case.
Since for 20% of the rise time have Length of the stub as 0.6 inches, which is greater than the rise time
value o.5nsec. Thus we can approximately say that Maximum length of the stub can be kept as as high
as 15% of the rise time
TD = 15 % of rise time
Here, rise time = 0.5 ns, so TD = 0.5 ns * 15 / 100 = 0.075 ns
So, the Maximum electrical length = 6inches/nsec * 0.075 = 0.45 inches
Thus actual length of the stub will be 0.45inches
Since 0.45 < 0.5 so it implies that Lstubmax < Rise Time
Thus at 15% of the rise time the reflection noise will be acceptable.
Figure 3.4.3: Schematics for Short stub reflections due to stub length 15% of the Rise Time and ideal
case (To keep reflection noise acceptable)
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Figure 3.4.4: Simulations for Short stub reflections due to stub length 15% of the rise time and ideal
case
Thus from the above graph we can see that maximum length of the stub should be 15% of the Rise time
that will keep the reflection noise acceptable.
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5. Re-create diagrams in Figure 8-23, page 312, for a transmission line end-terminated in three
capacitance values 2pF, 5pF and 10pF. What is modeled by these capacitances? Give several
examples. Can you estimate the new rise times (at the beginning and end of TL) and the increase in
time delay for these specific cases? How do your calculations compare to your simulation results?
Reflections due to capacitive load
Figure 3.5.1: Schematics for reflections due to varying capacitive load
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Figure 3.5.2: Simulations for reflections due to varying capacitive load
If the rise time is short compared to the charging time of the capacitor, then initially, the voltage will rise
up very fast and the impedance will be low. But as the capacitor charges, the voltage across it gets
smaller and dV/dt slows down. The exact behavior will depend on the characteristic impedance of the
line (Z0), the capacitance of the capacitor and the rise time of the signal.
Thus this capacitors in the circuit model to the “RC circuit” behavior where C is the capacitance of the
load and R is the characteristic impedance of the transmission line, Z0.
Calculation of Rise Time for 2pF, 5pF, 10pF:
We have the formula from eqn. (8-20)
RT = 2.2 * Z0 * C
RT2pF = 2.2 * 50 * 2 = 0.22 nsec
RT5pF = 2.2 * 50 * 5 = 0.55 nsec
RT10pF = 2.2 * 50 * 10 = 1.1 nsec
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Calculation of Time Delay for 2pF, 5pF, 10pF:
We know that Total Capacitance is given by =
For 2pF
Time Delay is TD = CT ∗ Z0 = 2 ∗ 50 = 0.1
For 5pF
Time Delay is TD = CT ∗ Z0 = 5 ∗ 50 = 0.25
For 10pF
Time Delay is TD = CT ∗ Z0 = 10 ∗ 50 = 0.5
Thus from our simulation graphs it is clear that the higher the capacitor the higher the rise time the
higher the time delay. Thus our calculations show the similar results as that of the simulations.
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6. Re-create diagrams in Figure 8-24, page 314, for a transmission line with capacitive load in the
middle of a trace for three capacitance values: 2pF, 5pF and 10pF. Calculate the maximum capacitance
for a specific rise-time and transmission line impedance. Compare the value with your simulations.
What should be done to keep capacitive discontinuities from causing excessive undershoot noise?
Reflection from Capacitive Loads in the Middle of a Trace
Fig. 3.6.1: Schematic with three different capacitance values
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Fig. 3.6.2: Simulation results due to varying capacitive discontinuity
Maximum allowable capacitance for a rise time of .5nsec and 50Ω transmission line impedance is 2pF.Asit is clear from the simulation results capacitance above 2pF has more discontinuities.
In order to keep capacitive discontinuities from causing excessive undershoot noise ,keep the
capacitance less than four times the rise time (rise time in nsec).
For a line with characteristic impedance of 50 Ω, Maximum allowable rise time for a capacitive
discontinuity is given as = 4 ∗
Maximum capacitance for rise time of 0.5 ns, = 4 ∗ 0.5 = 2
For 0.5 nsec, maximum allowable capacitance is 2 pF. For 0.5 nsec rise time, capacitance above 2pF will
have more undershoot problems
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7. Re-create diagrams in Figure 8-34, page 329, for a transmission line with inductive load in the
middle of a trace for three inductance values: 1nH, 5nH and 10nH. What is the maximum acceptable
inductive discontinuity for this example? Compare calculations and simulations. How can we
compensate this series inductance, if its large value is unavoidable? Propose a solution and simulate
it.
Reflections from Inductive Discontinuities
Fig. 3.7.1: Schematic with three different inductive discontinuity
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Fig. 3.7.2: Simulation Results for reflections due to varying inductive discontinuity
Maximum allowable inductive discontinuity is given as < 0.2 ∗ 0 ∗ Lmax< .2*50*50
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Compensation circuit for an inductive discontinuity
Fig. 3.7.3: Compensation Schematic
Fig. 3.7.4: Simulation results
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