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Interview Question Bank on ATPG & SCAN
Questions
1- What is ATPG?
2- What is Scan Insertion and Scan Chain?
3-What is Full and Partial Scan?
4-What is Combbinational ATPG and
Seuential ATPG?
Which has less !atterns? Wh"?
#- Wh" $e use Combo% ATPG &or &ull scan ?
'- What is Fault Co(era)e and Test Co(era)e?
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*- +,!lain dierent Fault .odels?
Stuc/ at &ault0 Transition &ault0 I &ault0Path dela" Fault% rid)un) &ault And e,!lain
the dierence bet$een stuc/ at and transition
&aults%
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- 5o$ "ou started anal"sin) co(era)e?
6-What is hierachical re!ort?
17- Wh" some 8o!s le&t non-scanned?
11-5o$ did "ou )et co(era)e on non-scanned-
!aths?
12-What is 9no-&aults9 ?
5o$ "ou can sa" that "ou can 9no-&ault9
somethin)? What about the co(era)e o& that
area?
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13- 5o$ "ou co(ered com!le, 9combo-lo)ic9
bloc/s? :; ho$ "ou )ot &ull controlabilt" and
:bser(anilit" on com!le, combo%
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1- What do "ou do $hile !er&ormin) 8o!-
stichin) there are some ne)ati(e ed)e and
some !oseti(e ed)e based 8o!s? 5o$ "ou $il
handle this situation?
16% +,!lain $hat is &ault colla!sin) ?
+,!lain in terms o& &ault dominance andFault eui(alence%
27% I& scan $as &ailin) and "ou slo$ do$n the
cloc/ and it starts to !ass $hat $as the cause
o& the &ailure in the be)innin)? Setu! or 5old
time?
21%Gi(e three im!ortant Cloc/ drc rules andho$ to =, them?
22%What is STI< !rocedure =le? What does it
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contains?
23% What is scannabilit" chec/in) or Scan inte-
)rit"? 5o$ "ou chec/ it?
24% 5o$ im!ortant is scan chain balancin) in
FT? 5o$ it eects in desi)ns i& the chains ar
not balanced?
2#%
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2'% Which 8o!s to a(oid &or scan?
2*%5o$ do $e ma/e sure that each 8o! is
)ettin) cloc/ and reset? Is a se!arate test clo
used or it is the &unctional cloc/?
2% 5o$ to decide the number o& chains?
26% ierence bet$een normal 8o! and
scan 8o!?
37% What is To! o& ATPG?
31% Wh" don9t $e add buer instead o&
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33%What is the dierence bet$een de&ect0
&ault and &ailure?
34%5o$ $e a!!l" i>!9s durin) simulation time
and durin) AT+ time?
OR
What is serial loadin) and !arallel loadin)?
3#%5o$ reset aected in co(era)e?
OR
Wh" did $e a!!lied reset &ro to! le(el?
3'% What is bloc/ le(el ATPG?
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3*% +,!lain about Fault Classes?.ention the Fault Class 5ierarch"%
3% What is Controlabilit" and :bser(abilit"?
36%What is
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co(era)e0less !atterns and better controlabil-
it"?
Why we go for MBIST?
41%Wh" in com!are to
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what are wrapper chains?
what is asi! "atterns # si$u%ate "atterns?
How technology impacts '(%?
'ow to get !overage on reset "in?
what is the difference between pre drc check and postdrc check in '(% compiler ?
Why there is difference in the pattern count and testcoverage between the two methods) *+$ and *+??
'ow to !over the fau%ts on inter !%o!k o$ain!rossing?
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Answers
ATPG is a automatic test pattern generation process which takes a gate-
level netlist along with some i/o constraints, clock defnitions, scan def-
nitions and generates a test patterns which can be used to fnd manuact-
uring deects in a real silocon!
"t also produces a ault coverage report that tells #ou how good #our test
is and which are covered and non covered nets b# test patterns!
The process o replacing ordinar# se$uential element into a scan se$uen-
tial element or the sake o better controlabilit# and observabilit# b#
adding scan signals %&',&(",&(O) and mu* and making it into scannable
element is called &can "nsertion! And the series o scannable se$uential
elements stitched together is called &can +hain!
elements then the test architecture is know as ull-scan
due to some reasons then the test architecture is known as partial-scan!
the se$uential elements in the ull scan design , so we can see the combo
! ogic between the se$uential elements, &o the ATPG tool take this
combo logic into consideration and generates combo patterns !
This is also a reason wh# no! o patterns are less in +ombo! ATPG!
the two scan .s there are non-scan .s along with the combo logic!
&o onl# combo patterns are not enough or them we re$uired se$uential
patterns or them! This is the reason ATPG tool has to generate patterns
with multiple clock pulses!
&o pattern count and runtime is much more than combo ATPG!
" all the se$uential elements are converted into scannable se$uential
elements into the design then the design is eectivel# reduced to a
combo! Onl# sets o circuits surrounded b# primar# i/o.s!
This simplifcation allows the combo! ATPG tool to be used in more
eective wa#!
ault +overage- A test pattern should target ever# possible aults in the
design but at times it might not to be possible to target ever# possible
ault in the design!
The ratio o aults targeted to the possible no! o aults is called as
ull &can- " all the se$uential elements are converted into scannable
Partial &can- " some non-scanned se$uential elements are let in design
+ombinational ATPG- The idea is to control and observe the values in all
&e$uential ATPG- 0e use this or partial scan design where between
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ault coverage!
either high1 or low2 is stucked on node!&o we want to detect that a particular node can toggle rom 2 to 1 and
1 to 2!
ensure that 2 to 1 and 1 to 2 happens but this time we have a time
constraint to see toggeling is happening in that given time constraint!
" it is not happening in certain amount o time then there is a transition-
ault!
&tuck at ault is what which is either connected to ground or vdd while in
transition ault i a node is not toggeling in certain amount o time thenwe can sa# that node is slow to rise or slow to all!
paths in our design
"t e*ercise the critical paths at-speed %the ull operating speed o chip)
to detect weather the path is too slow because o manuacturing deects
or variations!
"ncorrect feld o*cide thickness could lead to slower singal propagation,
which could cause transition along a critical path to arrive too late!
which causes two normall# unconnected singnal nets in a device to
become electricall# connected due to incorrect etching !
&uch deects can be detected i one o the nets causes the other net to
take on a ault# value!
this ault we need to measure the amount o current drawn b# a +3O&device in a $uiescent state!
+3O& circuits almost draws no current in $uiescent state! 4uiescent
means the i/o.s are stable and the circuit is inactive!
" circuit has designed correctl# the amount o curent is e*treme small in
$uiescent state and i signifcant amount o current is there then it
indicates the presence o one or more deects!
ault +overage5 aults detected/ Total no! o aults!
Test +overage5 aults detected/ (etectable aults
&tuck At ault- "t is a static check as the name suggests a particular value
Transition ault- 6ere the node is same, toggle is same ! we have to
Path (ela# ault- "s useul or testing and characterising critical timing
7ridging ault - 7ridging%or short) is common deect in semiconductor
"((4 ault- "t is a t#pe o ault which occurs in +3O& circuits! To detect
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" started working on given ault list! " picked up the list o those classes,
or e*ample A8%atpg untestable) so, A8 is the thing which bring down the
coverage thus " picked up A8 list and started to improvisation o coverage
and " observed one particular block so tried to reporting the hierachical-
report or that block!
&o rom the hierachical report " picked up the low coverage modules!" knew that i we improve coverage on block level it will directl# atect
at top level!
&o while " was observing one particular block which were having soman#
non-scanned 9ops!
&o, basicall# the tool was loosing controlabilit# and observabilit# here!
And that.s the reason we had low coverage or that block!
"t will report the hierachical# each and ever# modules coverage! &o that
rom that report we can anal#se which modules having low coverages!
There was certain issues with the critical path! " we do scan insertion itwill add e*tra mu* dela# in the data path which will bring down the
unctional re$uenc#!
And it was so critical i we add mu*es and all the# might not be able to
close the timing at whatever re$uired highspeed re$uenc#! &o we
decided to remove these 9ops rom the scan chain!
" started anal#sing and then " generated se$uential patterns or them!
" increased se$uential depth up to : and " was getting ma*imum path -
coverage or that particaular module!
&o its confrmed that because o non-scanned se$uential elements we
were loosing coverage!
Then " moved to other block and while an#al#sing " ound that most o
the part is covered b# memor# instances in a particular block!
&o i" did .no-aults. or it!
Tools will remove those aults rom the ault-list when we appl#
no-aults. to it!
&o basicall# it will reduce the number o aults which is going to be
targeted!
" we do .no-aults. so those aults are not going to be considered so
patterns wont be generated or that part! +onclusion is that our coverage
has increased but that area is untested!
7ut we cant leave such area untested so we know that or memories
we test them using 37"&T patterns likewise " we appl# .no-aults. or
;TAG , we know we have separate patterns .;TAG-patterns. which will test
it!
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0hile " was anal#sing " ound that there was huge combo logic and it was
not controllable and observable! 7ecause in that block the combo logic
was much more than the se$uential logic!
&o there was ver# ew 9ops, we cant put scain chain there in a eective
wa# so that the whole logic gets controlabilit# and observabilit#!
&o there was a need to put test points! 7asicall# two t#pes o test ponts
is there 1)- controlled low
reset pin and we constrained that reset to one!
Reset goes to each and ever# block and reset tied to 1!&o the whole logic got uncovered in stuck at 1 ault, because alwa#s tied
to 1!
&o, at the top o ATPG we run separate ATPG where we defned reset
as a clock! 0e didn?t added all the aults onl# undetected aults and then
we started generated patterns! Thus we covered those points due to
tied logic!
=es, non-transparent latches was the reason wh# some blocks were
getting low coverage!
7asicall# or the non-transparent latches clock is blocked them to be
transparent! As the# were not getting clock and we know that latches
should be leven sensitive!&o to avoid this issue we controlled clock or
top level!
&ummar# on +overage improvement
7# having controlabilit# and observabilit# on all the nets we can improve
our coverage! The issues with stops us to achive high coverage is listed
below!
1) @on-scanned 9ops!
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ets assume a scenario, there are two 9ops 1 and < and both asserted
b# dierent clock clk1 and clk
1 and < so there might be possibilit# that lauch and capture might
happen on the same pulse!
7ut i we add a lock up latch in between 1 and
additional time like hal clock c#cle so that now data will capture on
second c#cle!
"n such scenarios where in 9op stiching there are some negative edge and
positive edge based 9ops we will tie-up all negative edge frst and then
the positive edge second! 7# doing this we can avoid issues related with
data Bumping!
ault +ollapsing- "t is t#picall# reduces the total number o aults!
0e generall# classifes it in two t#pes -1)8ncollapsed aults C
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and other controls!
The &T" procedure fle can be generated rom (T +ompiler and we use
it in or (R+ checks!
The test procedure fle contains all the scan inormation o #our test
read# netlist! &ome other inormations mentioned below,
The number o scan cells in each scan chain!
The number o the scan chains!
The shit clocks!
The capture clocks!
The timing o the dierent clocks!
The time or orcing the Primar# input , bidi inputs , scan inputs etc !
The time to measure the primar# outputs, scan outputs etc!
The frst pattern that is pattern 2 in most o the ATPG tool is called the
the chain test pattern! This pattern is used to check the integrit# o thescan chains, to see i the scan chains are shiting and loading properl#,
i the scan chains itsel have a ault, there is no use checking the ull chip
using this chain!
Generall# FF!FF precent o test time %on the tester) is spent loading the
scan chains and this is directl# proportional to the length o the longest
scan chain in #our design! &o the wa# to minimie test time is to minimie
test time is to minimie the length o #our longest parallel chain!
7alancing the scan chain is critical because i #ou have scan 12 scan chains
and F chains has 12 9ops but the 12th chain has 122 9ops each shit has to
be 122 clock pulses and unnecessaril# the tool has to insert H or F2 clock
c#cles! so #our overall test time or one pattern will be 122 clock c#cles to
scan in, 122 to scan out and one capture c#cle! "t could have been 12 to
shit in, 12 to shit out and 1 capture c#cle! so #ou overall test time or
one pattern is
capture ailure!
! shit in all 1 to initialie the chain!
:! =ou shit in 22111111 and the capture passes! The cause o ailure
should be in the rd or :th 9ops because the rd and :th 9ops are onl#
9ops that change the value and can contribute to the capture ailure!
I! shit in all 1 to initialie the chain,
D! =ou shit in 22211111 and the capture ails! The the cause o ailure
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should be in the rd 9op!
&hit registers are t#picall# the onl# 9ops let out o the scan chain!
&ome reset and metastabilit# 9ops ma# make sense to leave o the scan
chains!
@OT'- An# 9ops that let out rom scain chain will need a separate
test suits or it!
"n order to be testable, ever# clock pin and ever# reset pin should be
controllable b# a primar# input during test mode!
(uring design #ou should run dt-rule-checks as part o #our s#nthesis
9ow! or high ault coverage, #ou should f* ever# dt warning/violation!
T#picall# the more scan chains #ou have the shorter #our tester test time
is! it takes less time to load 12222 9ops 2 %2 scan chains) each shit clock
than i #ou could onl# load < %< scan chains) each shit clock!
i #ou onl# have < seconds o test time to do all o #our testing #ou ma#
A scan 9ip 9op is ordinar# 9ip 9op modifed or sake o using it during dt!
"t has additional scan input and scan output or sending test inputs
and receiving test outputs!
@ormal lip-lop have (, +lk C 4!
&can 9op have (, &" %scan in), &' %scan enable), +lk, 4 and/or &O %scan out)
(uring scan shit operation %&'51), data will shit in through the &" pin!
(urig scan capture state %&'52), data will capture into scan 9op via ( pin!
0e generate combo! ATPG patterns or ull scan! 7ut or partial scan,
&till there are man# combo! Onl# paths so or them we will generate
combo! ATPG patters and then or the remaining logic we will generate
se$uential ATPG patters! This is called as Top o ATPG!
" #our skew is big, then #ou will need a lot o buers or dela# cells, which
is undesirable or power/area etc!
re$uenc# o operation is not as important during scan shiting! Therore,
we can alwa#s slow down the re$ and/or modi# the dut# c#cle to
remove a hold time problem with data lockup latches!
@ormall# test clocks have low re$uencies! At these re$uencies basicall#
#ou can check the connectivit# o the nets %e!g! shorts/opens)!
6owever #ou cannot see the real parasitic eects o a unctional clock
which has higher re$uenc# than test clocks!
fnd that #ou run out o test time!!!
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At this point using at-speed-clock, which means running the circuit at its
unctional re$uenc#, #ou can gather more inormation %e!g! path dela#)
and improve the coverage!
At speed test are used in anal#ing path dela#/transition dela# o circuit!
@ormal tests are good to test .stuck at. aults but the# ail in testingtiming behavior o circuits!
(eects J "mperection or 9aw that occurs within silicon!
aults J Representation o a deect!
ailures J @on-perormance o the intended unctions o the s#stem!
'*amples ,A ph#sical short is considered a (eect!
A ph#sical short resulting in stuck-at behavior might be modeled as a
stuck-at- 1/2 ault!
@on-perormance o the s#stem due to error is ailure!
&erial and Parallel patterns both are %and must be) same or a give scan
mode%"nternal or Adaptive)! The onl# dierence is in the wa# the# are
are applied on the design!
"n serial patterns,all the patterns are applied through &can"n and &canOut!
The operations are similar to the Tester environment!
7ut the parallel patterns are applied directl# to the internal registers,
thereore no &hit-in, shit-out! &o reduces the test time!
The direct access to registers is possible onl# in simulation environment
C hence Parallel patterns are used onl# in &imulations and @OT in tester!
The serial pattern is describing timing in realit#, and parallel patterns is
Bust to veri# the correctness o logic, not including timing!
"n our design we had active>low reset pin and we cconstrained that reset
to 1!
Reset goes to each and ever# block and it is tied to 1! &o, the whole logic
was not covered in stuck at 1 ault, because we had tied it to1!
&o, at the top o ATPG we run a separate ATPG, where we defned ATPG
as a clock!
0e didn?t added all the aults , onl# the undetected aults and when we
started generating patterns we covered those uncovered points due to
reset.s tied logic!
0e can describe block level as it is one o the core block o the ull chip
design! &uppose the ull chip contains : core blocks and we approached to
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improve coverage or a particulat block is called block level ATPG!
" we improve coverage at block level , automaticall# at chip level we are
going to have good coverage! &o that when we move rom block level to
top level we don?t have to spend much time to debug at top level!
aults are assigned to classes indicating their current ault detection ordetectabilit# status!A two character code is used to speci# a ault class!
ault +lass 6ierarch#-
(T - (etected
PT - Possibl# (etected
8( - 8ndetectable
A8 - ATPG 8ntestable
@( - @ot (etected
7asicall# ATPG 8ntestable is the main reason behind low coverage!
+ontrollabilit#J 0e can control the internal part through stimulus!
Observabilit#J 0e can monitor the internal part variation through output
interace to writing testbench!
The two most popular transition tests are O& and O+!
The# are categoried b# how the# launch transition b# launching on shit
or b# launching on capture!
O&-aunch on &hit- 0hen the last shit on the scain chain load is used to
launch the transition then we call it a launch on shit operation!
0here launch is happening on shiting path and capturing on unctional
path!
O+-aunch on +apture- The launch o transition is done in capture mode
when scan enable is 2!
0here both launch and shit happening on unctional path!
O&-
Advantages-
3ore coverage!ess patterns!
7asic +ombo ATPG used!
(isadvantage-
&can 'nable &' signal has to be ver# ast! This might not possible in ever#
scenario! "t re$uires ast clock domain signals that could be used to launch
and capture transition $uickl#!
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O+-
Advantage-
@o need o &can 'nable &' signal to be ver# ast!
(isadvantages-
ess coverage!
3ore patterns!&e$uential algorithm used!
O& is combo based algorithm, because there is onl# one c!p! during the
capture mode! @o second needs to be stored b# ATPG to determine how
the circuit will react ater the second clock pulse!
That is the reason wh# it has less patterns and more coverage with
controlabilit#!
O+ is se$uential based algorithm, 7ecause it is essentiall# a double
capture and the ATPG tool needs to be able to store the state o the circuit
ater the last shit and frst clock pulse o capture in order to know whatis e*pected ater the second capture !
That is the reason wh# it has more patterns but less coverage compared to
O&!
Though controlabilit# diers but Observabilit# is same in both O& C O+!
inkedin 4uestion
"t is depend on tool , like tetra ma* use onl# verilog lib !&ome ATPG tool use their ownlib! There are same , no dierence! And ATPG lib are vendor specifc!
or some reasons we have to do block level patteren generation !%1) To check that what is the test coverage we have achived at block level! " the
coverage is low then we can add the test points and increase the coverage! &ame wecan do it at top level directl# it might be ver# diKcult!
0e will consider highest re$uec# amoung that to test memor#!And i dual port memor#
working with as#nchonous re$uenc# then we can gurentee that unctionalit# wiseboth will work fne!
1) i we do memor# checking with ATPG wa# the we re$uire lots o shit c#cle to shitthe address and data to the respective pins , shit c#cle increase , tester time increaseand chip cost increase!
%
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"t is made up o wrapper cells! "t is like envelope to isolate the some block or "P&! Tob#pass tha logic , wrapper chain is used , it increase the controlibilit# and obserbilit#!
the top level or not% &1 and &< rule violation in (TA(L"O&'R ) !PO&T (R+JJ "t will checks
that the there is no an# blockage in scan chain!
"n O& , means launching event happen in the shit path , here we have ullcontrollabilt# to load our desire vaules in the scan chains , and the ater directl#capture the response so here coverage is more!
O+JJJ aunch on capture , means the
capture event happend in to the capture path , so here the patterns are comming rothe data path so here controlibilt# is less so , coverage is less and to the coverperticular ault it has to tr# more to detect that perticluar ault so patterns are more!
0e make path as aulse path which are inter clock doamin crossing! &o we don?t testaults on those paths!
IDDq test becomes more difficult due to the leakage gets higher.Size of chip will decrese.
step%1) (efne reset as clock! %
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Additional details on answers or corrections
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