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ROUTING &TRACKING SYSTEMFOR MOBILEVEHICLESIN LARGE AREA
Presented by:
Y.Lavanya(08MR1A0458)
T.Sunil(08MR1A0453)
P.Hepsi(08MR1A0445)
P.Shyambabu(08MR1A0438)
Guided by:Mr.K.Ramakrishna M.tech
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CONTENTS
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INTRODUCTION
The system permits localization of the automobile
and transmitting the position to the owner on his
mobile phone as a short message (SMS) at his
request.
This tracking system is composed of a GPS
receiver, PSOC fabricated with Accelerometer
sensor and a GSM Modem.
GPS Receiver gets the location information from
satellites in the form of latitude and longitude.
PSOC processes .
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BLOCK DIAGRAM
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POWER SUPPLY
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CPU SUBSYSTEM
ARM Cortex-M3
Industrys leading embedded CPU company
Broad support for middleware and applications
Up to 80 MHz; 100 DMIPS
Enhanced v7 ARM architecture:
Thumb2 Instruction Set
16- and 32-bit Instructions (no mode switching)
32-bit ALU; Hardware multiply and divide
Single cycle 3-stage pipeline; Harvard architecture
8051
Broad base of existing code and support
Up to 67 MHz; 33 MIPS
Single cycle instruction execution
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CPU SUBSYSTEM
High Performance Memory
Flash memory with ECC
High ratio of SRAM to flash
EEPROM
Powerful DMA Engine
24-Channel Direct Memory Access Access to all Digital and Analog Peripherals
CPU and DMA simultaneous access to independent
SRAM blocks
On-Chip Debug and Trace
Industry standard JTAG/SWD (Serial Wire Debug)
On chip trace
NO MORE ICE
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CPU SUBSYSTEM
Clocking System
Many Clock Sources Internal Main Oscillator
External clock crystal input
External clock oscillator inputs
Clock doubler output
Internal low speed oscillator
External 32 kHZ crystal input Dedicated 48 MHz USB clock
PLL output
16-bit Clock Dividers
8 Digital
4 Analog
PSoC Creator Configuration Wizard PSoC Creator auto-derive clocking source/dividers
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CPU SUBSYSTEM
Dedicated Communication Peripherals
Full Speed USB device
8 bidirectional data end points + 1 control end point
No external crystal required
Drivers in PSoC Creator for HID class devices
Full CAN 2.0b
16 RX buffers and 8 TX buffers
I2C master or slave
Data rate up to 400 kbps
Additional I2C slaves may be implemented in UDB
array
New peripherals will be added as family members are
added to the platform: Ethernet, HS USB, USB Host
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CPU SUBSYSTEM
Power Management
Industrys Widest Operating Voltage 0.5V to 5.5V with full analog/digital capability
High Performance at 0.5V
PSoC 3 @ 67 MHz; PSoC 5 @ 72 MHz
3 Power Modes (Active, Sleep and Hibernate)
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DESIGNEDFOR LOW POWER/LOW VOLTAGE
Integrated Analog, Digital and
Communication PeripheralsReduce external component counts and lower overall
system power consumption
Universal Digital BlocksImplement features in
hardware that reduce CPU
processing requirements,
lowering power consumption
Precise CPU frequenciesPLL allows 4,032 different
frequencies; tunable power
consumption
On-board DMA Controller
Direct memory transfer betweenperipherals offloads CPU operation,
lowering power consumptionHighly configurable clock treeFlexible, automated clock gating.
Cached OperationsExecution from flash memory is
improved by caching
instructions (PSoC 5 only)
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LOW POWER MODES
Power mode Current(PSoC 3)
Current(PSoC 5)
Codeexecution
Digital
resources
available
Analog
resources
available
Clock sourcesavailable
Wakeupsources
Resetsources
Active1.2 mA
@ 6MHz
2 mA
@ 6MHzYes All All All N/A All
Sleep 1 uA 2 uA No I2C ComparatorLow Speed and
32 kHz Osc
IO, I2C,
RTC,
sleep timer,
comparator
XRES, LVD,
WDR
Hibernate 200 nA 300 nA No None None None IO XRES, LVD
Power Management Enabled in PSoC Creator
Provides easy to use control APIs for quick power management
Allows code and register manipulation for in-depth control
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GSM
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GPS
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LCD DISPLAY
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EEPROM
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RELAY
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ADVANTAGES
Ease of maintenance
Less power consumption
Alert message to mobile phone for remote
information
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APPLICATIONS
Security
Remote monitoring
Transportation and logistics
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CONCLUSION
In this project work, we have studied and
implemented a complete working model using a
Microcontroller. The programming and interfacing of
microcontroller has been mastered during the
implementation.