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Page 1: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

2010/12/10

R. Minami , Tokyo tech.

Measurement of Integrated PA-to-LNA Isolation on Si CMOS Chip

Ryo Minami , JeeYoung Hong ,Kenichi Okada , and Akira Matsuzawa

Tokyo Institute of Technology, Japan

Page 2: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

2

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

Outline

• Tx leakage and problem• Evaluation of Tx leakage

– Tx leakage paths– Measurement and Simulation method

• Result• Conclusion

Page 3: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

3

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

Background

• Merit– High frequency characteristic– High supply voltage

• Demerit– Chip area and cost

CMOS transistors can provide a sufficient performance for PA design.

The level of Tx leakage increases.

To investigate Tx leakage paths.

Conventionally, Power Amplifier (PA) has been implemented by compound semiconductors.

CMOS technology has been developed.

Page 4: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

4

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

Tx leakage and problem

FDD system

• The large transmitted signal leaks to Rx input side.• Tx leakage causes IM and degrades demodulation quality.

Tx leakage

interference signal

Rx signal

cross modulation

intermodulation distortion

Tx leakage

interference signal

Rx signal

LNA nonlinearity

Duplexer

PA

transmitted signal

received signal

LNATx

leakage

Page 5: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

5

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

Tx leakage paths

substrate couplinginductor couplingwire coupling (Vdd, GND)

conventional single-chip

The integration of the PA with other blocks increases many coupling paths.

Duplexer

LNA

PA

Duplexer

LNA

PA

Page 6: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

6

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

p+ n+n+ p+ n+n+

- +gnd VDD

PA LNA- +

p+ n+n+

gnd VDD

Air gap

Magnetic

p+ n+n+ p+ n+n+

- +gnd VDD

MagneticPA LNA- +

p+ n+n+

gnd VDD

Substrate coupling

Dicing

Substrate coupling and inductor coupling are generated because PA and LNA are integrated on the same chip.

Substrate coupling is blocked by physically separating the PA and LNA[1].

[1] J.Y. Hong et al., IEICE society Conference, 2009.

Page 7: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

7

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

Measurement method

• substrate coupling

• inductor coupling• inductor coupling

After dicing, the distance between PA and LNA is 0.74mm, 1.55mm, 2.37mm, 3.20mm.

afterbeforesubstrate dicingdicingcouplingGainGainSisolation

)(]dB[ LNAPA21

Chip

probe probe

absorber

Network Analyzer

PA LNA1 LNA2 LNA3 LNA4

-5dBm

Chip

absorber

probeair gap

PA

probe

Network Analyzer

LNA1 LNA2 LNA3 LNA4

-5dBm

PA LNA

input output

isolation

S21

GLNAGPA

On-Chip

Page 8: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

8

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

Specification of the designed PA and LNA

PA

LNA

PA LNATechnology 0.18 m CMOS processFrequency 5 GHz

VDD 3.3 V 1.8 VGain at 5 GHz 5.5 dB 15.1 dBNF at 5 GHz 2.7 dB

Area 1.01mm×1.01mm 0.70mm×1.01mm

Page 9: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

9

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

Simulation methodMagnetic coupling simulation by HFSS (an electromagnetic    field simulator)

Circuit simulation with magnetic coupling effect by goldengate

The magnetic coupling between the inductor at PA output side and the inductor at LNA input side is the most dominant.

Assume

On-chip50 W

input

output

3.3 V

1.8 V

Magnetic coupling

PA LNA

PAinductor

LNAinductor

distance

104m

(1.5 turn)

(2.5 turn)

160m0.74mm1.55mm2.37mm3.20mm

Page 10: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

10

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

Simulation result

• Gain of PA and LNA are shown at 5 GHz

• S21 depends on the distance between PA and LNA

-160

-140

-120

-100

-80

-60

-40

0 1 2 3 4 5 6 7 8 9 10Frequency[GHz]

S 21[

dB]

0.74mm 1.55mm2.37mm 3.2mm

Gain of PA and LNA

Page 11: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

11

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

-160

-140

-120

-100

-80

-60

-40

0 1 2 3 4 5 6 7 8 9 10frequency[GHz]

S 21 [

dB]

0.74mm 1.55mm2.37mm 3.2mm

sim.: dotted

meas.: solid

-160

-140

-120

-100

-80

-60

-40

0 1 2 3 4 5 6 7 8 9 10frequency[GHz]

S 21 [

dB]

0.74mm 1.55mm2.37mm 3.2mm

sim.: dotted

meas.: solid

noise flooror

thermal noise

probe coupling

• Under 3 GHz– Thermal noise from the resistance of LNA– Noise floor of the network analyzer

• Around 5 GHz– Noise floor of the network analyzer with gain

• Over 8 GHz– Probe coupling exists.

Assume

Measurement result

Page 12: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

12

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

Noise floor and probe coupling● Noise floor ● Probe coupling

Network Analyzer

open(=S21)

3cm

probe probe

2cm

absorber

-5dBm

S21 with 3 cm distance between probes and 2cm distance between probe and absorber

Noise floorS21 with 4 patterns of probe distance and 0.3mm distance between probe and absorber

Probe coupling

Network Analyzer

coupling(=S21)

0.98mm,1.8mm,2.62mm,3.45mm

0.3mmabsorber

-5dBm

probe probe

Page 13: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

13

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

Probe coupling problem● The case of measuring chip

● The case of measuring probe coupling

Signal flows into the chip.

This is the worst case of probe coupling.

Chip

probe probe

PA LNA

couplingsignal

signal

absorberGND

probe probe

absorber

couplingsignal

0.3mm

Page 14: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

14

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

Thermal noise from the resistance of LNA

outcableLNALNAthermal NALossGainNFTBNoise )k(Log10]dB[ 

: noise calculation pointNetwork Analyzer

PA LNAinput output

×(a)

GLNAGPA

On-Chip

-5dBm

k: 1.38*10-23 [J/K]T: 300 [K]

B: 10 [Hz]Cable loss:2 [dB]

Page 15: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

15

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

Result of error analysis (higher and lower side)

-160

-140

-120

-100

-80

-60

-40

0 1 2 3 4 5 6 7 8 9 10frequency[GHz]

S 21&

Ther

mal

noi

se [d

B]

0.74mmprobe coupingnoise floornoise NA

thermal

• Under 3 GHz– Noise floor of the network analyzer

• Over 8 GHz– Probe coupling exists.

Page 16: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

16

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

• Around 5 GHz– Noise floor of network analyzer with gain

Result of error analysis (middle section)

dB80)GHz5( LNAPA GainGainnoisefloor

-160

-140

-120

-100

-80

-60

-40

0 1 2 3 4 5 6 7 8 9 10frequency[GHz]

S 21 [

dB]

0.74mm1.55mm2.37mm3.2mmnoise floor

GPA+GLNA

sim.: dottedmeas.: solid

Page 17: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

17

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

Comparison of coupling data at 5 GHz

-120

-110

-100

-90

-80

-70

-60

-50

-40

0 1 2 3 4distance[mm]

Isol

atio

n [d

B]

inductor coupling

simulation

noise floor

-120

-110

-100

-90

-80

-70

-60

-50

-40

0 1 2 3 4distance[mm]

Isol

atio

n [d

B]

all Tx leakageinductor couplingsubstrate coupling

Duplexer isolation

• The isolation value of inductor coupling is affected by the noise floor of the NA over 1.8mm distance between PA and LNA.

• Total isolation value becomes smaller than that of the duplexer over 0.4mm

• Substrate coupling is the most dominant factor in Tx leakage.

Page 18: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

18

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

Conclusion

• Substrate coupling is the most dominant factor in Tx leakage for Si substrate.

• Total isolation value becomes smaller than that of the duplexer over 0.4mm distance between PA and LNA.

• Error sources in measurement are noise floor of the network analyzer and probe coupling.

Page 19: [PPT]スライド 1 · Web viewMeasurement of Integrated PA-to-LNA Isolation on Si CMOS Chip Ryo Minami,JeeYoung Hong,Kenichi Okada,and Akira Matsuzawa Tokyo Institute of Technology,

2010/12/10

R. Minami , Tokyo tech.

19

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa

& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology

Thank you for your attention!