PERSISTENCE: I/O DEVICES
Shivaram Venkataraman CS 537, Spring 2019
ADMINISTRIVIA
Project 4a: Out tonight, due on April 4th Work in groups of up to two Grades: Project 2b, 3, midterm by tomorrow!
AGENDA / LEARNING OUTCOMES
How does the OS interact with I/O devices? What are the components of a hard disk drive?
RECAP
OPERATING SYSTEMS: THREE EASY PIECES
Three conceptual pieces
1. Virtualization
2. Concurrency
3. Persistence
VIRTUALIZATION
Make each application believe it has each resource to itself CPU and Memory
Abstraction: Process API, Address spaces Mechanism:
Limited direct execution, CPU scheduling Address translation (segmentation, paging, TLB)
Policy: MLFQ, LRU etc.
CONCURRENCY
Events occur simultaneously and may interact with one another Need to
Hide concurrency from independent processes Manage concurrency with interacting processes
Provide abstractions (locks, semaphores, condition variables etc.) Correctness: mutual exclusion, ordering Performance: scaling data structures, fairness Common Bugs!
OPERATING SYSTEMS: THREE EASY PIECES
Three conceptual pieces
1. Virtualization
2. Concurrency
3. Persistence
Motivation
What good is a computer without any I/O devices?keyboard, display, disks
We want:
- H/W that will let us plug in different devices
- OS that can interact with different combinations
Why use hierarchical buses?
Hardware support for I/O
Canonical Device
OS reads/writes to these
Status COMMAND DATADevice Registers
Example Write Protocol
while (STATUS == BUSY) !; // spin !
Write data to DATA register !Write command to COMMAND register !while (STATUS == BUSY) !
; // spin !
Status COMMAND DATA
Microcontroller (CPU+RAM) Extra RAM Other special-purpose chips
while (STATUS == BUSY) // 1 !; !
Write data to DATA register // 2 !Write command to COMMAND register // 3 !while (STATUS == BUSY) // 4 !
; !
CPU:
Disk:
2 3,4
A BCPU:
Disk: C A
B B AA
1
while (STATUS == BUSY) // 1 !
wait for interrupt; !
Write data to DATA register // 2 !
Write command to COMMAND register // 3 !
while (STATUS == BUSY) // 4 !
wait for interrupt; !
Interrupts!
Interrupts vs. Polling
Are interrupts always better than polling? Fast device: Better to spin than take interrupt overhead
– Device time unknown? Hybrid approach (spin then use interrupts) Flood of interrupts arrive
– Can lead to livelock (always handling interrupts) – Better to ignore interrupts while make some progress handling them
Other improvement – Interrupt coalescing (batch together several interrupts)
Protocol Variants
Status checks: polling vs. interrupts
Status COMMAND DATA
Microcontroller (CPU+RAM) Extra RAM Other special-purpose chips
DATA TRANSFER COSTS
Programmed I/O vs. Direct Memory Access
PIO (Programmed I/O):– CPU directly tells device what the data is
DMA (Direct Memory Access):
– CPU leaves data in memory
– Device reads data directly from memory
while (STATUS == BUSY) // 1 !; !
Write data to DATA register // 2 !Write command to COMMAND register // 3 !while (STATUS == BUSY) // 4 !
; !
ACPU:
Disk: C A
B B A
1 3,4
Protocol Variants
Status checks: polling vs. interrupts
PIO vs DMA
Status COMMAND DATA
Microcontroller (CPU+RAM) Extra RAM Other special-purpose chips
while (STATUS == BUSY) // 1 !; !
Write data to DATA register // 2 !Write command to COMMAND register // 3 !while (STATUS == BUSY) // 4 !
; !
Status COMMAND DATA
Microcontroller (CPU+RAM) Extra RAM Other special-purpose chips
Special Instructions vs. Mem-Mapped I/O
Special instructions– each device has a port– in/out instructions (x86) communicate with device
Memory-Mapped I/O
– H/W maps registers into address space
– loads/stores sent to device
Doesn’t matter much (both are used)
Protocol Variants
Status checks: polling vs. interrupts
PIO vs DMA
Special instructions vs. Memory mapped I/O
Status COMMAND DATA
Microcontroller (CPU+RAM) Extra RAM Other special-purpose chips
Storage Stack
application file system scheduler
driver hard drive
build common interface on top of all HDDs
DEVICE DRIVERS
Variety is a Challenge
Problem:– many, many devices– each has its own protocol
How can we avoid writing a slightly different OS for each H/W combination?
Write device driver for each device
Drivers are 70% of Linux source code
BUNNY 10
https://tinyurl.com/cs537-sp19-bunny10
BUNNY 10
If you have a fast non-volatile memory based storage device, which approach would work better?
What part of a device protocol is improved by using DMA ?
HARD DISKS
HARD DISK INTERFACE
Disk has a sector-addressable address space Appears as an array of sectors
Sectors are typically 512 bytes Main operations: reads + writes to sectors Mechanical and slow (?)
Platter
Surface
Surface
Spindle
RPM?
Motor connected to spindle spins platters
Rate of rotation: RPM 10000 RPM à single rotation is 6 ms
Surface is divided into rings: tracks Stack of tracks(across platters): cylinder
123
065 4
789
1011
1514
1312
16
17
18
19
23
22
21
20
Tracks are divided into numbered sectors
123
065 4
789
1011
1514
1312
16
17
18
19
23
22
21
20
Heads on a moving arm can read from each surface.
READING DATA FROM DISK
Rotational delay
READING DATA FROM DISK
Seek Time
Time to Read/write
Three components: Time = seek + rotation + transfer time
Seek, Rotate, Transfer
Seek cost: Function of cylinder distance Not purely linear cost Must accelerate, coast, decelerate, settle Settling alone can take 0.5 - 2 ms
Entire seeks often takes 4 - 10 ms Average seek = 1/3 of max seek
Depends on rotations per minute (RPM) 7200 RPM is common, 15000 RPM is high end Average rotation?
Pretty fast: depends on RPM and sector density. 100+ MB/s is typical for maximum transfer rate
BUNNY 11
https://tinyurl.com/cs537-sp19-bunny11
BUNNY
What is the time for 4KB random read?
NEXT STEPS
Advanced disk features Scheduling disk requests Project 4a: Out tonight Grades: Project 2b, 3, midterm by tomorrow!
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