Download - Part III Lectures 15-18 Field-Effect Transistors (FETs ... 1/… · University of Technology Field-Effect Transistors (FETs) Electrical and Electronic Engineering Department Lecture

Part III Lectures 15-18

Field-Effect Transistors (FETs) and Circuits

University of Technology Field-Effect Transistors (FETs) Electrical and Electronic Engineering Department Lecture Fifteen - Page 1 of 8

Second Year, Electronics I, 2009 - 2010 Dr. Ahmed Saadoon Ezzulddin

G

D

S

Gate (G)

Drain (D)

Source (S)

n-c

hann

el

p p

S

G

D

S

G

D

p-c

hann

el

n n

Field-Effect Transistors (FETs) Basic Definitions: The FET is a semiconductor device whose operation consists of controlling the flow of current through a semiconductor channel by application of an electric field (voltage). There are two categories of FETs: the junction field-effect transistor (JFET) and the metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET category is further broken-down into: depletion and enhancement types. A Comparison between FET and BJT:

FET is a unipolar device. It operates as a voltage-controlled device with either electron current in an n-channel FET or hole current in a p-channel FET.

BJT made as npn or as pnp is a current-controlled device in which both electron current and hole current are involved.

The FET is smaller than a BJT and is thus for more popular in integrated circuits (ICs).

FETs exhibit much higher input impedance than BJTs. FETs are more temperature stable than BJTs. BJTs have large voltage gain than FETs when operated as an amplifier. The BJT has a much higher sensitivity to changes in the applied signal (faster

response) than a FET. Junction Field-Effect Transistor (JFET): The basic construction of n-channel (p-channel) JFET is shown in Fig. 15-1a (b). Note that the major part of the structure is n-type (p-type) material that forms the channel between the embedded layers of p-type (n-type) material. The top of the n-type (p-type) channel is connected through an ohmic contact to a terminal referred to as the drain "D", while the lower end of the same material is connected through an ohmic contact to a terminal referred to as the source "S". The two p-type materials are connected together and to the gate "G" terminal. (a) (b)

Fig. 15-1



D

p p DDV

GGV+

−GSV

+

−DSV

S

GAIG 0=

DI

n

Depletion regions

Electronflow

Basic Operation of JFET:

Bias voltages are shown, in Fig. 15-2, applied to an n-channel JFET devise. VDD provides a drain-to-source voltage, VDS, (drain is positive relative to source) and

supplies current from drain to source, ID, (electrons move from source to drain). VGG sets the reverse-bias voltage between the gate and the source, VGS, (gate is

biased negative relative to the source). Input impedance at the gate is very high, thus the gate current IG = 0 A. Reverse biasing of the gate-source junction produces a depletion region in the

n-channel and thus increases its resistance. The channel width can be controlled by varying the gate voltage, and thereby, ID

can also be controlled. The depletion regions are wider toward the drain end of the channel because the

reverse-bias voltage between the gate and the drain is grater than that between the gate and the source.

Fig. 15-2 JFET Characteristics:

When VGS = 0 V and VDS < PV (pinch-off voltage)*: ID rises linearly with VDS (ohmic region, n-channel resistance is constant), as shown in Fig. 15-3.

∗ When VDS is increased to a level where it appears that the two depletion regions

would "touch", a condition referred to as pinch-off will result. The level of VDS that establishes this condition is referred to as the pinch-off voltage and is denoted by VP.



D

p p

S

G

DSSI

n

PDS VV ≥

+

_VVGS 0=+

_

DSSI

V0

)(mAID

)(VDSPV

Saturation level

VVGS 0=

D

p p

S

G

DI

n

PDS VV <

+

_VVGS 0=+

_

DSSI

)(mAID

Increasing resistance dueto narrowing channel

)(VVDS

n-channel resistance

0PV

Fig. 15-3

When VGS = 0 V and PDS VV ≥ : ID remains at its saturation value IDSS beyond VP, as shown in Fig. 15-4.

Fig. 15-4

When VGS < 0 and VDS some positive value: The effect of the applied negative-bias VGS is to establish depletion regions similar to those obtained with VGS = 0 V but at lower levels of VDS. Therefore, the result of applying a negative bias to the gate is to reach the saturation level at lower level of VDS, as shown in Fig. 15-5.

Fig. 15-5



Summary: For n-channel JFET: 1. The maximum current is defined as IDSS and occurs when VGS = 0 V and PDS VV ≥

as shown in Fig. 15-6a. 2. For gate-to-source voltages VGS less than (more negative than) the pinch-off level,

the drain current is 0 A (ID = 0 A) as appearing in Fig. 15-6b. 3. For all levels of VGS between 0 V and the pinch-off level, the current ID will range

between IDSS and 0 A, respectively, as shown in Fig. 15-6c. (a) (b)

(c)

Fig. 15-6 For p-channel JFET a similar list can be developed (see Fig. 15-7).

Fig. 15-7



Shockley's Equation: For the BJT the output current IC and input controlling current IB were related by β, which was considered constant for the analysis to be performed. In equation form: control variable ↓ BC II ⋅= β ↑ constant

In the above equation a linear relationship exists between IC and IB. Unfortunately, this linear relationship does not exist between the output (ID) and input (VGS) quantities of a JFET. The relationship between ID and VGS is defined by Shockley's equation: control variable ↓

2

1 ⎟⎟⎠

⎞⎜⎜⎝

⎛−=

P

GSDSSD V

VII [15.1]

↑______↑____ constant

The squared term of the equation will result in a nonlinear relationship between ID and VGS, producing a curve that grows exponentially with decreasing magnitude of VGS. Transfer Characteristics: Transfer characteristics are plots of ID versus VGS for a fixed value of VDS. The transfer curve can be obtained from the output characteristics as shown in Fig. 15-8, or it can be sketched to a satisfactory level of accuracy (see Fig. 15-9) simply using Shockley's equation with the four plot points defined in Table 15-1.

Fig. 15-8



PV

DSSI

2/DSSI

4/DSSI

PV5.0 PV3.0

)(mAID

)(VVGS0

Table 15-1

2

1 ⎟⎟⎠

⎞⎜⎜⎝

⎛−=

P

GSDSSD V

VII

VGS (V) ID (mA) 0 IDSS

0.3 VP IDSS / 2 0.5 VP IDSS / 4

VP 0 Fig. 15-9 Important Relationships: A number of important equations and operating characteristics have introduced in the last few sections that are of particular importance for the analysis to follow for the dc and ac configurations. In an effort to isolate and emphasize their importance, they are repeated below next to a corresponding equation for the BJT. The JFET equations are defined for the configuration of Fig. 15-10a, while the BJT equations relate to Fig. 15-10b. (a) (b)

Fig. 15-10 JFET BJT

2

1 ⎟⎟⎠

⎞⎜⎜⎝

⎛−=

P

GSDSSD V

VII ⇔ BC II β=

SD II = ⇔ EC II ≅ AIG 0≅ ⇔ VVBE 7.0≅



Transconductance Factor: The change in drain current that will result from a change in gate-to-source voltage can be determined using the transconductance factor gm in the following manner: GSmD VgI Δ⋅=Δ The transconductance factor, gm, (on specification sheets, gm is provided as yfs) is the slop of the characteristics at the point of operation, as shown in Fig. 15-11. That is,

.constVGS

Dfsm

DSVIyg

=ΔΔ

==

Fig. 15-11 An equation for gm can be derived as follows:

22

.

11 ⎟⎟⎠

⎞⎜⎜⎝

⎛−=

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛−==

− P

GS

GSDSS

P

GSDSS

GSptQGS

Dm V

VdV

dIVVI

dVd

dVdIg

⎥⎦

⎤⎢⎣

⎡−⎥

⎦

⎤⎢⎣

⎡−=⎟⎟

⎠

⎞⎜⎜⎝

⎛−⎥

⎦

⎤⎢⎣

⎡−=

PP

GSDSS

P

GS

GSP

GSDSSm VV

VIVV

dVd

VVIg 1012112

⎥⎦

⎤⎢⎣

⎡−=

P

GS

P

DSSm V

VVIg 12

[15.2]

and

P

DSSm V

Igo

2= [15.3]

where is the value of gm at VGS = 0 V. omg

Equation [15.2] then becomes:

⎥⎦

⎤⎢⎣

⎡−=

P

GSmm V

Vggo

1 [15.4]

JFET Output Impedance: The output impedance (rd) is defined on the drain (output) characteristics of Fig. 15-12 as the slope of the horizontal characteristic curve at the point of operation. In equation form:

.

1

constVD

DS

osd

GSI

Vy

r=Δ

Δ== [15.5]



where yos is the output admittance, with the units of μS, as appear on JFET specification sheets.

Fig. 15-12 JFET AC Equivalent Circuit: The control of Id by Vgs is include as a current source gmVgs connected from drain to source as shown in Fig. 15-13. The current source has its arrow pointing from drain to source to establish a 180o phase shift between output and input voltages as will as occur in actual operation. The input impedance is represented by the open circuit at the input terminals and the output impedance by the resistor rd from drain to source.

g

s

d

dr

s

gsmVg

dI

+

−dsV

+

_gsV

Fig. 15-13 Exercises: 1. Sketch the transfer curve defined by IDSS = 12 mA and VP = − 6 V.

2. For a JFET with IDSS = 8 mA and VP = − 4 V, determine:

a. the maximum value of gm (that is, omg ), and

b. the value of gm at the following dc bias points: VGS = − 0.5 V, VGS = − 1.5 V, and VGS = − 2.5 V.

3. Given yfs = 3.8 mS and yos = 20 μS, sketch the JFET ac equivalent model.

University of Technology DC Biasing Circuits of JETs Electrical and Electronic Engineering Department Lecture Sixteen - Page 1 of 8


+

−GSV

+

−DSV

DC Biasing Circuits of JFETs 1. Fixed-Bias Configuration: For the circuit of Fig. 16-1, , AIG 0≅and . VRIV GGRG

0== For the input circuit, , 0=−− GSGG VVand GGGS VV −= Fig. 16-1 From Shockley's equation:

2

1 ⎟⎟⎠

⎞⎜⎜⎝

⎛−=

P

GSDSSD V

VII

For the output circuit, , 0=−− DSDDDD VRIVand DDDDDS RIVV −= A graphical analysis is shown in Fig. 16-2. Fig. 16-2 Example 16-1: For the circuit of Fig. 16-1 with the following parameters: IDSS = 10 mA, VP = − 8 V, VDD = + 16 V, VGG = 2 V, RG = 1 MΩ, and RD = 2 kΩ, determine the following: VGSQ, IDQ, VDS, VD, VG, and VS. Solution: From Fig. 16-3:

VVV GGGSQ 2−=−= , and . mAI DQ 6.5=

DDDDDS RIVV −= Vkm 8.4)2)(6.5(16 =−= .

VVV DSD 8.4== . VVV GSG 2−== .

VVS 0= . Fig. 16-3



Self-bias line

2. Self-Bias Configuration: For the circuit of Fig. 16-4, , AIG 0≅and . VRIV GGRG

0== , DS II =and V . SDR RI

S=

For the input circuit, , 0=−−

SRGS VVand SDGS RIV −= Fig. 16-4 From Shockley's equation:

2

1 ⎟⎟⎠

⎞⎜⎜⎝

⎛−=

P

GSDSSD V

VII

For the output circuit, 0=−−−

SD RDSRDD VVVV , and )( SDDDDDS RRIVV +−= A graphical analysis is shown in Fig. 16-5. Fig. 16-5 Example 16-2: For the circuit of Fig. 16-4 with the following parameters: IDSS = 8 mA, VP = − 6 V, VDD = + 20 V, RG = 1 MΩ, RS = 1kΩ, and RD = 3.3 kΩ, determine the following: VGSQ, IDQ, VDS, VG, VS, and VD. Solution: Choosing , we obtain mAI D 4=

.4)1)(4( VkmRIV SDGS −=−=−= At the Q-point (see Fig. 16-6):

VVGSQ 6.2−= , and . mAI DQ 6.2=)( SDDDDDS RRIVV +−=

Vkkm 82.8)3.31)(6.2(20 =+−= . VVG 0= , and VkmRIV SDS 6.2)1)(6.2( === .

VkmRIVV DDDDD 42.11)3.3)(6.2(20 =−=−= , Fig. 16-6 or V .42.116.282.8 VVV SDSD =+=+=



2C

1C

Example 16-3 (Common-Gate Configuration): For the common-gate configuration of Fig. 16-7, determine the following: VGSQ, IDQ, VD, VG, VS, and VDS.

Fig. 16-7 Solution: Choosing , we obtain VmAID 6= .08.4)680)(6( VmRI SDGS −=−=−= At the Q-point (see Fig. 16-8): V VGSQ 6.2−≅ , and mAI DQ 8.3≅ .

VkmRIVV DDDDD 3.6)5.1)(8.3(12 =−=−= . VVG 0= .

VmRIV SDS 58.2)680)(8.3( === . VVVV SDDS 72.358.23.6 =−=−= .

Fig. 16- 8



Example 16-4 (Design): For the circuit of Fig. 16-9, the levels of VDQ and IDQ are specified. Determine the required values of RD and RS.

Fig. 16-9 Solution:

Ω=−

=−

== kmI

VVIV

RDQ

DQDD

DQ

RD

D 2.325

1220 .

Plotting the transfer curve as shown in Fig. 16-10 and drawing a horizontal line at IDQ = 2.5 mA will result in VGSQ = − 1 V, and applying SDGS RIV −= will establish the level of RS :

Ω=−−

=−

= kmI

VR

DQ

GSQS 4.0

5.2)1( .

Fig. 16-10



Voltage-divider bias line

3. Voltage-Divider Bias Configuration: For the circuit of Fig. 16-11, , AIG 0≅ ⇒

21 RR II =

and 21

2

RRRVV DD

G +⋅

= .

For the input circuit, , 0=−−

SRGSG VVV , SDSSR RIRIV

S==

and SDGGS RIVV −= Fig. 16-11 From Shockley's equation:

2

1 ⎟⎟⎠

⎞⎜⎜⎝

⎛−=

P

GSDSSD V

VII

For the output circuit, 0=−−−

SD RDSRDD VVVV , and )( SDDDDDS RRIVV +−= A graphical analysis is shown in Fig. 16-12. Fig. 16-12 Example 16-5: For the circuit of Fig. 16-11 with the following parameters: IDSS = 8 mA, VP = − 4 V, VDD = + 16 V, R1 = 2.1 MΩ, R2 = 270 kΩ, RD = 2.4 kΩ, and RS = 1.5 kΩ, determine the following: VGSQ, IDQ, VD, VS, VDS, and VDG. Solution:

VkM

kRRRVV DD

G 82.12701.2

)270)(16(

21

2 =+

=+⋅

= .

)5.1(82.1 kIRIVV DSDGGS −=−= , when : mAID 0= VVGS 82.1= , and

when : VVGS 0= mAk

I D 21.15.182.1

== .

At the Q-point (see Fig. 16-13): VVGSQ 8.1−= , and . mAI DQ 4.2=

Fig. 16-13



VkmRIVV DDDDD 24.10)4.2)(4.2(16 =−=−= . VkmRIV SDS 6.3)5.1)(4.2( === .

VkkmRRIVV SDDDDDS 64.6)5.14.2)(4.2(16)( =+−=+−= , or . VVVV SDDS 64.66.324.10 =−=−=

VVVV GDDG 42.882.124.10 =−=−= . Example 16-6 (Two Supplies): Determine the following for the circuit of Fig. 16-14; VGSQ, IDQ, VDS, VD, and VS.

Fig. 16-14 Solution: For the input circuit of Fig. 16-14,

0=+−− SSSSGS VRIV (KVL) and , AIG 0≅ ⇒ SD II = SDSSGS RIVV −=

)5.1(10 kIV DGS −= , for ; , and mAID 0= VVGS 10=

for ; VVGS 0= mAk

I D 67.65.1

10== .

At the Q-point (see Fig. 16-15): VVGSQ 35.0−= , and . mAI DQ 9.6=

For the output circuit of Fig. 16-14, 0=+−−− SSSSDSDDDD VRIVRIV ,

)( SDDSSDDDS RRIVVV +−+= Fig. 16-15 VkkmVDS 23.7)5.18.1)(9.6(1020 =+−+= .

VkmRIVV DDDDD 58.7)8.1)(9.6(20 =−=−= . VVVV DSDS 35.023.758.7 =−=−= .



Example 16-7 (p-channel JFET): Determine VGSQ, IDQ, and VDS for the p-channel JFET of Fig. 16-16.

Fig. 16-16 Solution:

Vkkk

RRRVV DD

G 55.46820

)20)(20(

21

2 −=+

−=

+⋅

= .

)8.1(55.4 kIRIVV DSDGGS +−=+= , when : mAI D 0= VVGS 55.4−= , and

when : VVGS 0= mAk

I D 53.28.1

)55.4(=

−−= .

At the Q-point (see Fig. 16-17): VVGSQ 4.1= , and mAI DQ 4.3= . VkmRRIVV SDDDDDS 7.4)8.17.2)(4.3(20)( −=++−=++−= .

Fig. 16-17



Exercises:

1. For the common-drain (source-follower) configuration of Fig. 16-18, determine the following: VGSQ, IDQ, VD, VG, VS, VDG, and VDS.

DDV V9+

ΩM1GRSR Ωk2.2

1C

2CiV

oV

mAIDSS 16=VVP 4−=

Fig. 16-18

2. For the voltage-divider bias configuration of Fig. 16-19, if VD = 12 V and VGS = − 2 V, determine the value of RS.

Fig. 16-19

University of Technology JFET Small-Signal Analysis Electrical and Electronic Engineering Department Lecture Seventeen - Page 1 of 7


DDV+

GR

DR

SR

sigR+

−sV

GC

SC

LR

CC

+

−oV

+

−iV

D

S

G

iZ

oZ oZ ′

oI

iI

LRgsmVg

sigR

+

−sV GR

+

−gsV dr

+

−oV

g

s

d

+

−iV

oIiI

oZ oZ ′iZDR

JFET Small-Signal Analysis Common-Source Configuration: The common-source configuration circuit of Fig. 17-1 includes a source resistor (RS) that may or may not be bypassed by a source capacitor (CS) in the ac domain.

Fig. 17-1 Bypassed (absence of RS): For the ac equivalent circuit of Fig. 17-2,

Fig. 17-2 Input impedance: Gi RZ = Output impedance: Approximate (neglecting rd); Exact (including rd); (for ) Do RZ = Dd Rr 10≥ dDo rRZ = DLo RRZ =′ dDLoLo rRRZRZ ==′



LR

gsmVgsigR

+

−sV

GR

dr+

−oV

g d

+

−iV

oIiI

oZiZ

s

+

−gsV

SR

DR

Voltage gain: Approximate (neglecting rd); Exact (including rd); )( DLgsmo RRVgV −= , )( dDLmv rRRgA −= , igs VV =

)( DLmi

ov RRg

VVA −==

sigi

iv

s

i

i

o

s

ov RZ

ZAVV

VV

VVA

s +⋅=⋅==

Current gain:

L

iv

i

oi R

ZAIIA ⋅−==

Phase relationship:

The negative sign in the resulting equation for Av reveals that a 180o phase shift occurs between the input and output signals.

Unbypassed (include of RS): For the approximate ac equivalent circuit ( Ω∞≈dr ) of Fig. 17-3,

Fig. 17-3 Output impedance: For , , with VVi 0= gsmRo VgII

D=+ SRoVVRgs RIIVV

DiS)(

0+−=−=

=,

so that SRomRo RIIgIIDD

)( +−=+ , or )1()1( SmRSmo RgIRgID

+−=+ , and .

DRo II −= Since , Then DRo RIV

D−= DoDoo RIRIV =−−= )( , and

Do

oo R

IVZ ==



DDV+

GRSR

sigR+

−sV

GC

CC

LR+

−oV

+

−iV

D

S

G

iZ

oZ

oI

iI

LR

gsmVgsigR

+

−sV GR

dr

+

−oV

g d

+

−iV oI

iI

oZ

iZ

s

+

−gsV

SR

Voltage gain: )( DLgsmo RRVgV −= => VSgsmisggs RVgVVVV −=−= gsSmi VRg )1( +=

Sm

DLm

i

ov Rg

RRgVVA

+−==

1)(

Common-Drain (Source-Follower) Configuration: The common-drain (source-follower) configuration circuit is shown in Fig. 17-4.

Fig. 17-4 For the ac equivalent circuit of Fig. 17-5,

Fig. 17-5 Input impedance: [high] Gi RZ = Output impedance: For , VVi 0= SodoRrgsmo RVrVIIVgI

Sd+=+=+ =>

( ) gsmSdoo VgRrVI −+= 11 , with VVogs iVV 0=−= => ( )mSdoo gRrVI ++= 11 ,



SRsigR+

−sV

SC

LR

CC

+

−oV

+

−iV

DS

GiZ

oZ

oIiI

DR

DDV

gsmVg

dr

+

−oV

g

d+

−iV

s−

+gsVSR DR

sigR

+

−sV iZ oZ

LR

oIiI

and ( )[ ]mSdooo gRrIVZ 11111 ++== => mSdo gRrZ /1= [low]

Sm

SmSo Rg

RgRZ+

==1

/1 (for dr 1≥ ) SR0

Voltage gain: )( dSLgsmo rRRVgV = , )( dSLgsmioisggs rRRVgVVVVVV −=−=−= => gsdSLmi VrRRgV )](1[ += ,

)(1

)(

dSLm

dSLm

i

ov rRRg

rRRgVVA

+== [less than 1]

)(1

)(

SLm

SLmv RRg

RRgA

+= (for ) Sd Rr 10≥

Phase Relationship: Vo and Vi are in-phase. Common-Gate Configuration: The common-gate configuration circuit is shown in Fig. 17-6.

Fig. 17-6 For the approximate ac equivalent circuit ( Ω∞≈dr ) of Fig. 17-7,

Fig. 17-7



DDV

1R

2R

DR

2SR

sigR

+

−sV

GC

SC

LR

CC

Ωk1Fμ10

ΩM1.2

Ωk270

Ωk4.2

Ωk2.1 Fμ20

Fμ20Ωk7.4

V16+

mV200

1SR Ωk3.0iZ

iI

oI

oZ oZ ′

Input impedance:

Sm

SmSi Rg

RgRZ+

==1

/1 [low] (Derive)

Output impedance: Do RZ =Voltage gain: )( DLgsmo RRVgV −= , and igs VV −= =>

)( DLmi

ov RRg

VVA ==

Phase Relationship: Vo and Vi are in-phase. Example 17-1 (Analysis): For the JFET amplifier circuit of Fig. 17-8 with parameter gm = 2.2 mS, determine: Zi, Zo, , Av = Vo/Vi, Ai = Io/Ii, oZ ′ sov VVA

s/= and . Assume . oV Dd Rr 10>

Fig. 17-8 Solution: Ω=== kMMRRZi 23927.01.221 . , Ω== kRZ Do 4.2 Ω===′ kkkRRZ DLo 59.14.27.4 .

11.2)3.0)(2.2(1

)59.1)(2.2(1

)(

1−=

+−=

+−=

kmkm

RgRRg

ASm

DLmv .



DDV

GR

DR

SR

sigR+

−sV

GC

SC

LR

CC

Fμ1.0

Fμ40ΩM10

V20+

Ωk6Fμ1.0

Ωk1

mV100

mAIDSS 10=VVP 4−=

1077.4

)239)(11.2(=

−−=−=

kk

RZAA

L

ivi .

vsigi

ivv A

kkk

RZZAA

s≈−=

+−

=+

= 10.21239

)239)(11.2( .

. mVmVAV svo s420)200(10.2 =−==

Example 17-2 (Design): Complete the design of the JFET amplifier circuit shown in Fig. 17-9 to have a voltage gain magnitude of 17.5 dB, using a relatively high level of gm for this device defined at VGSQ = VP/4. Assume . Dd Rr 10>

Fig. 17-9 Solution: , VVV PGSQ 14/44/ −=−==

mSmVV

VIg

P

GS

P

DSSm 75.3

411

4)10(212

=⎟⎠⎞

⎜⎝⎛

−−

−=⎟⎟⎠

⎞⎜⎜⎝

⎛−= ,

5.7log205.17log20)( 1010 =⇒=⇒= vvv AAAdBG , Ω=⇒=⇒= kRRkmRRgA DDDLmv 3)6(75.35.7)( .

mAmV

VII

P

GSQDSSDQ 625.5

411101

22

=⎟⎠⎞

⎜⎝⎛

−−

−=⎟⎟⎠

⎞⎜⎜⎝

⎛−= ,

Ω=⇒−=−⇒−= 178)(625.51 SSSDQGSQ RRmRIV .



Exercises:

1. For each one of the circuits shown in Fig. 17-10, determine: (a) VGS, and gm. (b) Zi, and Zo. (c) A iov VV /= , and . ioi IIA /=

DDV

GRSR

sigR+

−sV

GC

LR

CC

+

−oV

+

−iV

iZ oZ

oI

iI

V12+

ΩM2Ωk3.3 Ωk2.2

Fμ2.8Ωk5.0

Fμ2.8

mAI DSS 6=VVP 6−=

DDV

DR

SRsigR+

−sV

SCLR

CC

Fμ6.5

V18+

Fμ6.5Ωk1

+

−iV

+

−oV

VVP 4−=mAIDSS 5=

Ωk3.3

7.4

Ωk2.1

oZ

iZ

oI

iI

Ωk

(a) (b) Fig. 17-10

2. Choose the values of RD, RS, and RL for the JFET amplifier circuit of Fig. 17-11 that will result in a gain of 18.062 dB. Assume that IDSS = 8 mA, VP = −4 V, rd ≈ ∞ Ω, VDQ/VDD = 0.375, and IDQ/IDSS = 0.25. Calculate so VV / , and sketch Vo.

vAs=

DDV

DR

SRsigR

+

−sV

SCLR

CC

Fμ1

V16+

Fμ10Ωk1

SSV V1−tSin )102(50 3×π mV

+

−iV

+

−oV

Fig. 17-11

University of Technology Frequency Response of JFET Amplifiers Electrical and Electronic Engineering Department Lecture Eighteen - Page 1 of 5


DDV+

GR

DR

SR

sigR+

−sV

GC

SC

LR

CC

+

−oV

+

−iV

D

S

G oR

iR

eqR

Frequency Response of JFET Amplifiers Low-Frequency Response of JFET Amplifiers: The Capacitors CG, CC, and CS will determine the lower-cutoff frequency (fL) of the common-source JFET amplifier shown in Fig. 18-1, but the results can be applied to any JFET amplifier. For the cutoff-frequency of CG,

GCisig XRR =+ =>

Gisig

L CRRf

G )(21+

=π

where . Gi RR = For the cutoff-frequency of CC,

CCoL XRR =+ =>

CoL

L CRRf

C )(21+

=π

Fig. 18-1

where . Do RR = For the cutoff-frequency of CS,

SCeq XR = =>

Seq

L CRf

S π21

=

where mSeq gRR /1= . The lower-cutoff frequency, ],,.[

SCG LLLL fffMaxf =



DDV+

GR

DR

SR

sigR

+

−sV

GC

SC

LR

CCD

S

G

gsC

gdC

dsC

oWC

iWC

LRgsmVg

sigR

+

−sV oR oCiCiR

oV

iThRoThR

ii MgsWi CCCC ++=oo MdsWo CCCC ++=

+

−oThE

oThR

oC

iThR

+

−iThE iC

+

−gsV

High-Frequency Response of JFET Amplifiers: The analysis of the high-frequency response of the JFET amplifier is similar to that encountered for the BJT amplifier. As shown in Fig. 18-2, there are interelectrode and wiring capacitances that will determine the high-frequency characteristics of the amplifier. The capacitors Cgs and Cgd typically vary from 1 to 10 pF, while the capacitance Cds is usually quite a bit smaller, ranging from 0.1 to 1 pF.

Fig. 18-2

Since the circuit of Fig. 18-2 is an inverting amplifier, a Miller effect capacitance will appear in the high-frequency ac equivalent circuit appearing in Fig. 18-3. The cutoff frequencies defined by the input and output circuits can be obtained by first finding the Thevenin equivalent circuits for each section as shown in Fig. 18-3.

Fig. 18-3



DDV

GR

DR

SR

sigR+

−sV

GC

SC

LR

CC

+

−oV

+

−iV

D

S

G

Ωk7.4

Ωk1

Fμ5.0

Fμ2ΩM1

V20+

Ωk2.2

Fμ01.0Ωk10

For the input circuit,

iTh

H CRf

ii π2

1=

and GsigTh RRR

i= .

with gdvgsWMgsWi CACCCCCCiii

)1( −++=++= . For the output circuit,

oTh

H CRf

oo π2

1=

and DLTh RRR

o= .

with gdvdsWMdsWo CACCCCCCooo

)/11( −++=++= . The higher-cutoff frequency, ],.[

oi HHH ffMinf = Example 18-1: For the JFET amplifier circuit shown in Fig. 18-4, with the following parameters: IDSS = 8 mA, VP = −4 V, rd > 10RD, Cgd = 2 pF, Cgs = 4 pF, Cds = 0.5 pF,

= 5 pF, and C = 6 pF. iWC

oW

a. Determine fL, fH, and BW. b. Sketch the frequency response.

Fig. 18-4



)(mAID

)(VVGS

8

4

0

Self-bias lineDGS IkV )1(−=

-4

VVGSQ 2−=-2

2

-3 -1

6

mAIDQ 2=

)( DSSI

)( PV

Q-point

Solution: From dc analysis (see Fig. 18-5):

VVGSQ 2−= , and , mAI DQ 2=

mSmV

VVIg

P

GSQ

P

DSSm 2

421

4)8(212

=⎟⎠⎞

⎜⎝⎛

−−

−=⎟⎟⎠

⎞⎜⎜⎝

⎛−= ,

3)7.42.2(2)( −=−=−= kkmRRgA DLmv .

HzMkCRR

fGGsig

LG16

)01.0)(110(21

)(21

≈+

=+

=μππ

, Fig. 18-5

HzkkCRR

fCDL

LC46

)5.0)(7.42.2(21

)(21

≈+

=+

=μππ

,

Ω=== 3.3335.01/1 kkgRR mSeq ,

HzCR

fSeq

LS239

)2)(3.333(21

21

≈==μππ

,

The lower-cutoff frequency, ],,.[SCG LLLL fffMaxf =

HzMax 239]239,46,16.[ == .

Ω≈== kMkRRR GsigThi9.9110 ,

pFpppCACCC gdvgsWi i17)2)(31(45)1( =+++=−++= ,

kHzpkCR

fiTh

Hi

i66.945

)17)(9.9(21

21

≈==ππ

,

Ω=== kkkRRR DLTho5.17.42.2 ,

pFpppCACCC gdvdsWo o17.9)2)(3/11(5.06)/11( =+++=−++= ,

MHzpkCR

foTh

Ho

o57.11

)17.9)(5.1(21

21

≈==ππ

,

The higher-cutoff frequency, ],.[oi HHH ffMinf =

kHzMkMin 66.945]57.11,66.945.[ == . The bandwidth, kHzkffBW LH 42.94523966.945 ≈−=−= .



The frequency response for the low- and high-frequency regions and bandwidth are shown in Fig. 18-6.

10 100 1k 10k 100k 1M 10M10

100M

dBAA

midv

v

f (log scale)- 5

- 10

- 15

BW

- 3 dB

GLf

CLfSLf

iHfLf HfoHf

Fig. 18-6 Exercise: For the JFET amplifier circuit of Fig. 18-7, determine the lower- and higher-cutoff frequencies and sketch the frequency response. DDV

1R

2R

DR

SR

sigR+

−sV

GC

SC

LR

CC

Ωk5.1Fμ1

Ωk220

Ωk68

Ωk9.3

Ωk2.2 Fμ10

Fμ8.6Ωk6.5

V20+

mAIDSS 10=VVP 6−=

pFCiW 3=

pFCoW 5=

pFCdg 4=pFCgs 6=pFCds 1=

Fig. 18-7